Up-down counter with direction control in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named count.

Verilog

reg [3:0] [1] ;

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Acount

Bclk

Cdir

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset names instead of the counter variable.

Forgetting to specify the bit width.

The register count holds the 4-bit counter value.

2fill in blank

medium

Complete the code to check if the reset signal is active high.

Verilog

if ([1]) begin
  count <= 4'b0000;
end

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Areset

Bclk

Cdir

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or direction signals instead of reset.

Not resetting the counter properly.

The reset signal is used to clear the counter to zero.

3fill in blank

hard

Fix the error in the always block sensitivity list to trigger on clock's positive edge.

Verilog

always @([1]) begin
  if (reset) count <= 4'b0000;
  else if (dir) count <= count + 1;
  else count <= count - 1;
end

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Anegedge clk

Bposedge reset

Cclk

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge' instead of 'posedge'.

Using the reset signal in sensitivity list incorrectly.

The always block should trigger on the positive edge of the clock signal.

4fill in blank

hard

Fill both blanks to complete the conditional increment and decrement of the counter.

Verilog

if (dir) count <= count [1] 1;
else count <= count [2] 1;

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A+

B-

C*

D/

Attempts:

3 left

💡 Hint

Common Mistakes

Using multiplication or division instead of addition or subtraction.

Mixing up increment and decrement operators.

The counter increments by 1 when direction is high, otherwise decrements by 1.

5fill in blank

hard

Fill all three blanks to complete the module header and port declarations for the up-down counter.

Verilog

module up_down_counter(
  input wire [1],
  input wire [2],
  input wire [3],
  output reg [3:0] count
);

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Aclk

Breset

Cdir

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Including 'enable' which is not used in this design.

Mixing up the order of inputs.

The module has inputs for clock, reset, and direction signals, and a 4-bit output count.