Synchronous vs asynchronous read in Verilog - Visual Side-by-Side Comparison

Concept Flow - Synchronous vs asynchronous read

Start

↓

Is read async?

Yes→Read data directly from memory

| No↓

Wait for clock edge

↓

Read data on clock edge

↓

Output data

↓

End

The flow shows that asynchronous read outputs data immediately, while synchronous read waits for a clock edge before outputting data.

Execution Sample

Verilog

module mem_read(
  input clk,
  input [3:0] addr,
  output reg [7:0] data_sync,
  output [7:0] data_async
);
  reg [7:0] mem [0:15];

  // Asynchronous read
  assign data_async = mem[addr];

  // Synchronous read
  always @(posedge clk) begin
    data_sync <= mem[addr];
  end
endmodule

This code shows a memory with both asynchronous and synchronous read ports.

Execution Table

Step	clk	addr	data_async	data_sync	Action
1	0	3	mem[3]	X	Initial state, clk=0, addr=3, async reads mem[3], sync data unknown
2	1 (rising edge)	3	mem[3]	mem[3]	Clock rises, synchronous read captures mem[3]
3	1	5	mem[5]	mem[3]	Addr changes to 5, async updates immediately, sync holds old data
4	0 (falling edge)	5	mem[5]	mem[3]	Clock falls, no sync update
5	1 (rising edge)	5	mem[5]	mem[5]	Clock rises, sync updates to mem[5]
6	1	2	mem[2]	mem[5]	Addr changes to 2, async updates immediately, sync holds old data
7	0 (falling edge)	2	mem[2]	mem[5]	Clock falls, no sync update
8	1 (rising edge)	2	mem[2]	mem[2]	Clock rises, sync updates to mem[2]
9	-	-	-	-	End of trace

💡 Trace ends after several clock cycles showing difference between async and sync read.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	Final
clk	0	1	1	0	1	1	0	1	1
addr	3	3	5	5	5	2	2	2	2
data_async	mem[3]	mem[3]	mem[5]	mem[5]	mem[5]	mem[2]	mem[2]	mem[2]	mem[2]
data_sync	X	mem[3]	mem[3]	mem[3]	mem[5]	mem[5]	mem[5]	mem[2]	mem[2]

Key Moments - 3 Insights

Why does data_sync not change immediately when addr changes?

Because data_sync updates only on the rising edge of clk, as shown in rows 3 and 6 of the execution_table where addr changes but data_sync holds old value until next clock.

Why does data_async change immediately when addr changes?

Because data_async is assigned directly from memory without waiting for clock, as seen in rows 3 and 6 where data_async updates instantly with addr.

What does 'X' mean for data_sync at start?

'X' means unknown or uninitialized value before first clock edge, as shown in step 1 of execution_table.

Visual Quiz - 3 Questions

Look at the execution_table at step 3. What is the value of data_sync?

A mem[3]

B mem[5]

C X

D mem[2]

💡 Hint

Check the 'data_sync' column at step 3 in execution_table.

At which step does data_sync first update to mem[5]?

A Step 3

B Step 5

C Step 6

D Step 2

💡 Hint

Look for the first step where data_sync equals mem[5] in execution_table.

If addr changes but clk does not rise, what happens to data_sync?

A It updates immediately

B It becomes unknown

C It stays the same

D It resets to zero

💡 Hint

Refer to steps 3 and 6 where addr changes but clk does not rise, data_sync remains unchanged.

Concept Snapshot

Synchronous read updates data only on clock edges (posedge clk).
Asynchronous read outputs data immediately when address changes.
Synchronous read uses 'always @(posedge clk)'.
Asynchronous read uses continuous assignment.
Synchronous read output may be delayed by one clock cycle.
Asynchronous read output changes instantly with address.

Full Transcript

This visual execution compares synchronous and asynchronous memory reads in Verilog. The asynchronous read outputs data immediately when the address changes, shown by data_async updating instantly. The synchronous read updates data only on the rising edge of the clock, so data_sync holds its value until the clock rises. Initially, data_sync is unknown (X) until the first clock edge. When the address changes without a clock edge, data_async changes immediately but data_sync remains the same. This shows the key difference: synchronous reads depend on clock timing, asynchronous reads do not.