Synchronous vs asynchronous read in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a synchronous read memory.

Verilog

reg [7:0] memory [0:15];
reg [3:0] addr;
reg [7:0] data_out;
always @(posedge clk) begin
  data_out <= memory[[1]];
end

Drag options to blanks, or click blank then click option'

Adata_out

Baddr

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as the memory index causes errors.

The synchronous read uses the address addr inside the clocked block to read memory.

2fill in blank

medium

Complete the code to declare an asynchronous read memory.

Verilog

reg [7:0] memory [0:15];
reg [3:0] addr;
wire [7:0] data_out;
assign data_out = memory[[1]];

Drag options to blanks, or click blank then click option'

Adata_out

Bmemory

Cclk

Daddr

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as the index causes errors.

For asynchronous read, the output data_out is assigned directly from memory at the address addr.

3fill in blank

hard

Fix the error in the synchronous read block to correctly read memory.

Verilog

always @(posedge clk) begin
  data_out <= memory[[1]];
end

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as index instead of addr.

The memory should be indexed by the address addr inside the clocked block.

4fill in blank

hard

Fill both blanks to create a synchronous read with address and clock signals.

Verilog

reg [7:0] memory [0:15];
reg [3:0] [1];
reg [7:0] data_out;
always @(posedge [2]) begin
  data_out <= memory[addr];
end

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up variable names or using data_out as address.

The address register is addr and the clock signal is clk.

5fill in blank

hard

Fill all three blanks to create an asynchronous read with address, output, and memory signals.

Verilog

reg [7:0] [1] [0:15];
reg [3:0] addr;
wire [7:0] [2];
assign [2] = [1][addr];

Drag options to blanks, or click blank then click option'

Amemory

Bdata_out

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk as memory or output name causes errors.

The memory array is named memory, and the output wire is data_out. The assignment reads from memory at addr.

Practice

1. Which statement best describes a synchronous read in Verilog?

easy

A. Data is updated randomly without clock control.

B. Data updates immediately when the address changes.

C. Data updates asynchronously with reset signal.

D. Data is updated only on the clock edge.

Solution

1. Step 1: Understand synchronous read behavior

   Synchronous read means data updates only at specific clock edges, not immediately.

2. Step 2: Compare with asynchronous read

   Asynchronous read updates data immediately when address changes, unlike synchronous read.

3. Final Answer:

   Data is updated only on the clock edge. -> Option D

4. Quick Check:

   Synchronous read = update on clock edge [OK]

Hint: Synchronous means wait for clock edge to update data [OK]

Common Mistakes:

• Confusing synchronous with asynchronous read
• Thinking data updates immediately in synchronous read
• Ignoring clock edge timing

2. Which Verilog code snippet correctly implements an asynchronous read from a memory array mem?

easy

A. assign data = mem[address];

B. always @(posedge clk) data <= mem[address];

C. always @(negedge clk) data <= mem[address];

D. always @(address) data <= mem[address];

Solution

1. Step 1: Identify asynchronous read syntax

   Asynchronous read uses continuous assignment to update data immediately when address changes.

2. Step 2: Check code options

   assign data = mem[address]; uses assign which is continuous and asynchronous. Others use clock or event triggers.

3. Final Answer:

   assign data = mem[address]; -> Option A

4. Quick Check:

   Asynchronous read uses assign statement [OK]

Hint: Use assign for asynchronous read, always block for synchronous [OK]

Common Mistakes:

• Using always block for asynchronous read
• Missing assign keyword for asynchronous read
• Triggering on clock edge for asynchronous read

3. Given the following Verilog code, what is the value of data after the clock edge if address changed just before the clock?

reg [7:0] mem [0:15];
reg [7:0] data;
always @(posedge clk) begin
  data <= mem[address];
end

medium

A. Data updates immediately when address changes.

B. Data updates only at the next clock edge with new address value.

C. Data never updates because address change is ignored.

D. Data updates asynchronously with address change.

Solution

1. Step 1: Analyze synchronous read behavior in code

   The always block triggers on clock edge, so data updates only then using current address.

2. Step 2: Consider address change timing

   Address changed just before clock, so data updates at clock edge with new address value.

3. Final Answer:

   Data updates only at the next clock edge with new address value. -> Option B

4. Quick Check:

   Synchronous read updates on clock edge [OK]

Hint: Synchronous read updates only on clock edge, not immediately [OK]

Common Mistakes:

• Assuming immediate data update on address change
• Ignoring clock edge timing
• Confusing asynchronous and synchronous read

4. Identify the error in this Verilog snippet intended for synchronous read:

reg [7:0] mem [0:15];
reg [7:0] data;
always @(address) begin
  data <= mem[address];
end

medium

A. The always block should trigger on clock edge, not address.

B. The memory array is declared incorrectly.

C. The data assignment should use blocking assignment (=) instead of non-blocking (<=).

D. The code is correct for synchronous read.

Solution

1. Step 1: Check sensitivity list for synchronous read

   Synchronous read requires triggering on clock edge, not on address change.

2. Step 2: Identify correct trigger

   The always block should use @(posedge clk) or similar clock edge trigger.

3. Final Answer:

   The always block should trigger on clock edge, not address. -> Option A

4. Quick Check:

   Synchronous read needs clock edge trigger [OK]

Hint: Synchronous always blocks trigger on clock edges only [OK]

Common Mistakes:

• Using address change in sensitivity list for synchronous read
• Confusing blocking and non-blocking assignments
• Incorrect memory declaration

5. You want to design a memory read module where data must be stable and updated only on clock edges, but the address can change anytime. Which approach should you use?

hard

A. Use asynchronous read with continuous assignment to data.

B. Use asynchronous read triggered by address change with non-blocking assignment.

C. Use synchronous read with data updated on clock edge from memory using address register.

D. Use combinational logic to update data immediately on address change.

Solution

1. Step 1: Understand requirement for stable data updated on clock edges

   Data stability and update only on clock edges means synchronous read is needed.

2. Step 2: Address can change anytime, so latch address and read memory synchronously

   Register the address on clock edge, then read memory synchronously to update data.

3. Final Answer:

   Use synchronous read with data updated on clock edge from memory using address register. -> Option C

4. Quick Check:

   Stable data + clock update = synchronous read with registered address [OK]

Hint: Register address and read data on clock edge for stable synchronous read [OK]

Common Mistakes:

• Choosing asynchronous read causing unstable data
• Not registering address before synchronous read
• Using combinational logic causing glitches