Synchronous vs asynchronous read in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a synchronous read memory.

Verilog

reg [7:0] memory [0:15];
reg [3:0] addr;
reg [7:0] data_out;
always @(posedge clk) begin
  data_out <= memory[[1]];
end

Drag options to blanks, or click blank then click option'

Adata_out

Baddr

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as the memory index causes errors.

The synchronous read uses the address addr inside the clocked block to read memory.

2fill in blank

medium

Complete the code to declare an asynchronous read memory.

Verilog

reg [7:0] memory [0:15];
reg [3:0] addr;
wire [7:0] data_out;
assign data_out = memory[[1]];

Drag options to blanks, or click blank then click option'

Adata_out

Bmemory

Cclk

Daddr

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as the index causes errors.

For asynchronous read, the output data_out is assigned directly from memory at the address addr.

3fill in blank

hard

Fix the error in the synchronous read block to correctly read memory.

Verilog

always @(posedge clk) begin
  data_out <= memory[[1]];
end

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or clk as index instead of addr.

The memory should be indexed by the address addr inside the clocked block.

4fill in blank

hard

Fill both blanks to create a synchronous read with address and clock signals.

Verilog

reg [7:0] memory [0:15];
reg [3:0] [1];
reg [7:0] data_out;
always @(posedge [2]) begin
  data_out <= memory[addr];
end

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cclk

Dmemory

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up variable names or using data_out as address.

The address register is addr and the clock signal is clk.

5fill in blank

hard

Fill all three blanks to create an asynchronous read with address, output, and memory signals.

Verilog

reg [7:0] [1] [0:15];
reg [3:0] addr;
wire [7:0] [2];
assign [2] = [1][addr];

Drag options to blanks, or click blank then click option'

Amemory

Bdata_out

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk as memory or output name causes errors.

The memory array is named memory, and the output wire is data_out. The assignment reads from memory at addr.