Synchronous vs asynchronous read in Verilog - Hands-On Comparison

Synchronous vs Asynchronous Read in Verilog

📖 Scenario: You are designing a simple memory module in Verilog. You want to understand the difference between synchronous and asynchronous read operations.This is important because synchronous reads happen on a clock edge, while asynchronous reads happen immediately when the address changes.

🎯 Goal: Build two small Verilog modules: one with asynchronous read and one with synchronous read. Then observe how the output changes based on the clock and address inputs.

📋 What You'll Learn

Create a memory array with 4 elements initialized to specific values

Implement an asynchronous read module using a combinational read

Implement a synchronous read module using a clocked process

Display the read data for both modules

💡 Why This Matters

🌍 Real World

Memory modules are fundamental in digital circuits. Understanding synchronous and asynchronous reads helps in designing efficient and reliable hardware.

💼 Career

Hardware engineers and FPGA developers often need to implement and debug memory blocks with different read behaviors.

1

Create a memory array with initial values

Create a 4-element memory array called mem of 8-bit registers. Initialize it with these values: 8'hAA, 8'hBB, 8'hCC, 8'hDD.

Verilog

// Declare a memory array called mem with 4 elements and initialize it
// Your code here

Need a hint?

Use reg [7:0] mem [0:3] to declare the memory array and initialize it with the given hex values.

2

Add address input and clock signal

Declare an input addr as a 2-bit wire and an input clk as a wire. These will be used to select memory location and clock the synchronous read.

Verilog

reg [7:0] mem [0:3] = {8'hAA, 8'hBB, 8'hCC, 8'hDD};
// Declare inputs addr (2-bit) and clk
// Your code here

Need a hint?

Use wire [1:0] addr; and wire clk; to declare the inputs.

3

Implement asynchronous and synchronous read outputs

Create two 8-bit registers: async_data and sync_data. Assign async_data to read from mem asynchronously using addr. Use an always @(posedge clk) block to assign sync_data synchronously from mem using addr.

Verilog

reg [7:0] mem [0:3] = {8'hAA, 8'hBB, 8'hCC, 8'hDD};
wire [1:0] addr;
wire clk;
// Declare async_data and sync_data registers
// Assign async_data asynchronously from mem using addr
// Use always @(posedge clk) to assign sync_data synchronously from mem using addr
// Your code here

Need a hint?

Use a combinational always @(*) block for asynchronous read and a clocked always @(posedge clk) block for synchronous read.

4

Display the asynchronous and synchronous read data

Write initial block to simulate and print the values of async_data and sync_data for addr values 0 to 3. Use $display to show the outputs. Assume clk toggles every 5 time units.

Verilog

reg [7:0] mem [0:3] = {8'hAA, 8'hBB, 8'hCC, 8'hDD};
wire [1:0] addr;
reg clk;

reg [7:0] async_data;
reg [7:0] sync_data;

always @(*) begin
    async_data = mem[addr];
end

always @(posedge clk) begin
    sync_data <= mem[addr];
end

// Create initial block to toggle clk and change addr from 0 to 3
// Use $display to print async_data and sync_data
// Your code here

Need a hint?

Toggle clk every 5 time units and increment addr on the rising edge. Use $display to print the time, address, async_data, and sync_data.