Synchronous vs asynchronous read in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of synchronous read in a RAM module

Consider the following Verilog code for a synchronous RAM read. What is the output value of data_out after the rising edge of clk when addr is 2?

Verilog

module sync_ram(input clk, input [1:0] addr, output reg [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'hAA;
    mem[1] = 8'hBB;
    mem[2] = 8'hCC;
    mem[3] = 8'hDD;
  end
  always @(posedge clk) begin
    data_out <= mem[addr];
  end
endmodule

A data_out = 8'hBB after the next rising edge of clk

B data_out = 8'hCC immediately at addr change

C data_out = 8'hCC after the next rising edge of clk

D data_out = 8'hDD immediately at addr change

💡 Hint

Think about when the data is updated in synchronous logic.

In synchronous RAM, the output data_out updates only on the rising edge of the clock. So when addr changes, data_out does not change immediately but updates after the next clock edge.

❓ Predict Output

intermediate

Output behavior of asynchronous read in a RAM module

Given the following Verilog code for an asynchronous RAM read, what is the value of data_out when addr changes to 3?

Verilog

module async_ram(input [1:0] addr, output [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'h11;
    mem[1] = 8'h22;
    mem[2] = 8'h33;
    mem[3] = 8'h44;
  end
  assign data_out = mem[addr];
endmodule

A data_out = 8'h44 immediately when addr changes

B data_out = 8'h33 after a clock edge

C data_out = 8'h22 after a clock edge

D data_out does not change until next clock edge

💡 Hint

Asynchronous read means output changes immediately with address.

In asynchronous RAM, the output data_out changes immediately when the address changes, without waiting for a clock edge.

🧠 Conceptual

advanced

Difference in timing between synchronous and asynchronous read

Which statement correctly describes the timing difference between synchronous and asynchronous RAM reads?

A Synchronous read updates output immediately when address changes; asynchronous read waits for clock edge

B Synchronous read updates output only on clock edge; asynchronous read updates output immediately when address changes

C Both synchronous and asynchronous reads update output only on clock edges

D Both synchronous and asynchronous reads update output immediately when address changes

💡 Hint

Think about when the output changes relative to the clock and address.

Synchronous read waits for the clock edge to update output, while asynchronous read updates output immediately when the address changes.

❓ Predict Output

advanced

Error type in mixed synchronous and asynchronous read code

What error will this Verilog code produce?

module mixed_ram(input clk, input [1:0] addr, output reg [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'h01;
    mem[1] = 8'h02;
    mem[2] = 8'h03;
    mem[3] = 8'h04;
  end
  always @(posedge clk) begin
    data_out <= mem[addr];
  end
  assign data_out = mem[addr];
endmodule

A Warning: unused variable mem

B No error, code runs correctly

C Runtime error: conflicting assignments

D SyntaxError: multiple drivers for data_out

💡 Hint

Check how data_out is assigned in both procedural and continuous assignments.

The code tries to assign data_out both inside an always block and with a continuous assign, causing multiple drivers error.

🧠 Conceptual

expert

Choosing read type for low-latency memory access

You need to design a memory module for a system that requires the fastest possible read access without waiting for a clock edge. Which read type should you choose and why?

A Asynchronous read, because it provides immediate data output on address change

B Synchronous read, because it ensures data stability on clock edges

C Synchronous read, because it avoids glitches on output

D Asynchronous read, because it synchronizes data with the clock

💡 Hint

Consider which read type updates output fastest after address changes.

Asynchronous read outputs data immediately when the address changes, providing the lowest latency. Synchronous read waits for clock edges, adding delay.