Synchronous vs asynchronous read in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of synchronous read in a RAM module

Consider the following Verilog code for a synchronous RAM read. What is the output value of data_out after the rising edge of clk when addr is 2?

Verilog

module sync_ram(input clk, input [1:0] addr, output reg [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'hAA;
    mem[1] = 8'hBB;
    mem[2] = 8'hCC;
    mem[3] = 8'hDD;
  end
  always @(posedge clk) begin
    data_out <= mem[addr];
  end
endmodule

A data_out = 8'hBB after the next rising edge of clk

B data_out = 8'hCC immediately at addr change

C data_out = 8'hCC after the next rising edge of clk

D data_out = 8'hDD immediately at addr change

💡 Hint

Think about when the data is updated in synchronous logic.

In synchronous RAM, the output data_out updates only on the rising edge of the clock. So when addr changes, data_out does not change immediately but updates after the next clock edge.

❓ Predict Output

intermediate

Output behavior of asynchronous read in a RAM module

Given the following Verilog code for an asynchronous RAM read, what is the value of data_out when addr changes to 3?

Verilog

module async_ram(input [1:0] addr, output [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'h11;
    mem[1] = 8'h22;
    mem[2] = 8'h33;
    mem[3] = 8'h44;
  end
  assign data_out = mem[addr];
endmodule

A data_out = 8'h44 immediately when addr changes

B data_out = 8'h33 after a clock edge

C data_out = 8'h22 after a clock edge

D data_out does not change until next clock edge

💡 Hint

Asynchronous read means output changes immediately with address.

In asynchronous RAM, the output data_out changes immediately when the address changes, without waiting for a clock edge.

🧠 Conceptual

advanced

Difference in timing between synchronous and asynchronous read

Which statement correctly describes the timing difference between synchronous and asynchronous RAM reads?

A Synchronous read updates output immediately when address changes; asynchronous read waits for clock edge

B Synchronous read updates output only on clock edge; asynchronous read updates output immediately when address changes

C Both synchronous and asynchronous reads update output only on clock edges

D Both synchronous and asynchronous reads update output immediately when address changes

💡 Hint

Think about when the output changes relative to the clock and address.

Synchronous read waits for the clock edge to update output, while asynchronous read updates output immediately when the address changes.

❓ Predict Output

advanced

Error type in mixed synchronous and asynchronous read code

What error will this Verilog code produce?

module mixed_ram(input clk, input [1:0] addr, output reg [7:0] data_out);
  reg [7:0] mem [0:3];
  initial begin
    mem[0] = 8'h01;
    mem[1] = 8'h02;
    mem[2] = 8'h03;
    mem[3] = 8'h04;
  end
  always @(posedge clk) begin
    data_out <= mem[addr];
  end
  assign data_out = mem[addr];
endmodule

A Warning: unused variable mem

B No error, code runs correctly

C Runtime error: conflicting assignments

D SyntaxError: multiple drivers for data_out

💡 Hint

Check how data_out is assigned in both procedural and continuous assignments.

The code tries to assign data_out both inside an always block and with a continuous assign, causing multiple drivers error.

🧠 Conceptual

expert

Choosing read type for low-latency memory access

You need to design a memory module for a system that requires the fastest possible read access without waiting for a clock edge. Which read type should you choose and why?

A Asynchronous read, because it provides immediate data output on address change

B Synchronous read, because it ensures data stability on clock edges

C Synchronous read, because it avoids glitches on output

D Asynchronous read, because it synchronizes data with the clock

💡 Hint

Consider which read type updates output fastest after address changes.

Asynchronous read outputs data immediately when the address changes, providing the lowest latency. Synchronous read waits for clock edges, adding delay.

Practice

1. Which statement best describes a synchronous read in Verilog?

easy

A. Data is updated randomly without clock control.

B. Data updates immediately when the address changes.

C. Data updates asynchronously with reset signal.

D. Data is updated only on the clock edge.

Solution

1. Step 1: Understand synchronous read behavior

   Synchronous read means data updates only at specific clock edges, not immediately.

2. Step 2: Compare with asynchronous read

   Asynchronous read updates data immediately when address changes, unlike synchronous read.

3. Final Answer:

   Data is updated only on the clock edge. -> Option D

4. Quick Check:

   Synchronous read = update on clock edge [OK]

Hint: Synchronous means wait for clock edge to update data [OK]

Common Mistakes:

• Confusing synchronous with asynchronous read
• Thinking data updates immediately in synchronous read
• Ignoring clock edge timing

2. Which Verilog code snippet correctly implements an asynchronous read from a memory array mem?

easy

A. assign data = mem[address];

B. always @(posedge clk) data <= mem[address];

C. always @(negedge clk) data <= mem[address];

D. always @(address) data <= mem[address];

Solution

1. Step 1: Identify asynchronous read syntax

   Asynchronous read uses continuous assignment to update data immediately when address changes.

2. Step 2: Check code options

   assign data = mem[address]; uses assign which is continuous and asynchronous. Others use clock or event triggers.

3. Final Answer:

   assign data = mem[address]; -> Option A

4. Quick Check:

   Asynchronous read uses assign statement [OK]

Hint: Use assign for asynchronous read, always block for synchronous [OK]

Common Mistakes:

• Using always block for asynchronous read
• Missing assign keyword for asynchronous read
• Triggering on clock edge for asynchronous read

3. Given the following Verilog code, what is the value of data after the clock edge if address changed just before the clock?

reg [7:0] mem [0:15];
reg [7:0] data;
always @(posedge clk) begin
  data <= mem[address];
end

medium

A. Data updates immediately when address changes.

B. Data updates only at the next clock edge with new address value.

C. Data never updates because address change is ignored.

D. Data updates asynchronously with address change.

Solution

1. Step 1: Analyze synchronous read behavior in code

   The always block triggers on clock edge, so data updates only then using current address.

2. Step 2: Consider address change timing

   Address changed just before clock, so data updates at clock edge with new address value.

3. Final Answer:

   Data updates only at the next clock edge with new address value. -> Option B

4. Quick Check:

   Synchronous read updates on clock edge [OK]

Hint: Synchronous read updates only on clock edge, not immediately [OK]

Common Mistakes:

• Assuming immediate data update on address change
• Ignoring clock edge timing
• Confusing asynchronous and synchronous read

4. Identify the error in this Verilog snippet intended for synchronous read:

reg [7:0] mem [0:15];
reg [7:0] data;
always @(address) begin
  data <= mem[address];
end

medium

A. The always block should trigger on clock edge, not address.

B. The memory array is declared incorrectly.

C. The data assignment should use blocking assignment (=) instead of non-blocking (<=).

D. The code is correct for synchronous read.

Solution

1. Step 1: Check sensitivity list for synchronous read

   Synchronous read requires triggering on clock edge, not on address change.

2. Step 2: Identify correct trigger

   The always block should use @(posedge clk) or similar clock edge trigger.

3. Final Answer:

   The always block should trigger on clock edge, not address. -> Option A

4. Quick Check:

   Synchronous read needs clock edge trigger [OK]

Hint: Synchronous always blocks trigger on clock edges only [OK]

Common Mistakes:

• Using address change in sensitivity list for synchronous read
• Confusing blocking and non-blocking assignments
• Incorrect memory declaration

5. You want to design a memory read module where data must be stable and updated only on clock edges, but the address can change anytime. Which approach should you use?

hard

A. Use asynchronous read with continuous assignment to data.

B. Use asynchronous read triggered by address change with non-blocking assignment.

C. Use synchronous read with data updated on clock edge from memory using address register.

D. Use combinational logic to update data immediately on address change.

Solution

1. Step 1: Understand requirement for stable data updated on clock edges

   Data stability and update only on clock edges means synchronous read is needed.

2. Step 2: Address can change anytime, so latch address and read memory synchronously

   Register the address on clock edge, then read memory synchronously to update data.

3. Final Answer:

   Use synchronous read with data updated on clock edge from memory using address register. -> Option C

4. Quick Check:

   Stable data + clock update = synchronous read with registered address [OK]

Hint: Register address and read data on clock edge for stable synchronous read [OK]

Common Mistakes:

• Choosing asynchronous read causing unstable data
• Not registering address before synchronous read
• Using combinational logic causing glitches