State diagram to Verilog translation - Step-by-Step Execution

Concept Flow - State diagram to Verilog translation

Start

↓

Define States

↓

Create State Encoding

↓

Write State Register

↓

Write Next State Logic

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Write Output Logic

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Simulate & Verify

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End

This flow shows how to translate a state diagram into Verilog code step-by-step, from defining states to writing logic and verifying.

Execution Sample

Verilog

typedef enum logic [1:0] {
  IDLE = 2'b00,
  WAIT = 2'b01,
  DONE = 2'b10
} state_t;

state_t state, next_state;

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= IDLE;
  else state <= next_state;
end

This code defines states and a state register that updates on clock or reset.

Execution Table

Step	Action	State Variable	Next State Logic	Output Logic	Notes
1	Define states IDLE, WAIT, DONE	state_t enum created	-	-	States encoded as 2-bit values
2	Initialize state register	state = IDLE	-	-	On reset, state set to IDLE
3	Evaluate inputs to decide next_state	state = IDLE	if start=1 then next_state=WAIT else IDLE	-	Transition from IDLE to WAIT on start signal
4	Update state on clock edge	state <= next_state	-	-	State changes at clock rising edge
5	Set outputs based on state	-	-	done=1 if state==DONE else 0	Output depends on current state
6	Check if state == DONE	state = DONE	next_state = IDLE	-	Return to IDLE after DONE
7	End simulation	-	-	-	All transitions covered

💡 Simulation ends after all states and transitions are verified.

Variable Tracker

Variable	Start	After Step 2	After Step 4	After Step 6	Final
state	undefined	IDLE	WAIT (if start=1)	DONE	IDLE (after DONE)
next_state	undefined	undefined	WAIT	IDLE	IDLE
done	0	0	0	1	0

Key Moments - 3 Insights

Why do we use a separate 'next_state' variable instead of updating 'state' directly?

Because 'state' updates only on the clock edge (step 4), 'next_state' holds the computed next state based on inputs (step 3). This separation avoids combinational loops and models synchronous behavior correctly.

How does the reset signal affect the state register?

At step 2, when reset is high, the state is forced to IDLE immediately, ensuring the FSM starts in a known state.

Why do outputs depend on the current state and not the next state?

Outputs are usually based on the current state (step 5) to reflect the FSM's present condition, ensuring stable and predictable output signals.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of 'state' after step 4 if 'start' is 1?

A WAIT

B IDLE

C DONE

D Undefined

💡 Hint

Refer to row 4 and variable_tracker for 'state' after step 4.

At which step does the FSM return to the IDLE state after completing the DONE state?

A Step 3

B Step 4

C Step 6

D Step 7

💡 Hint

Check the execution_table row describing transition from DONE to IDLE.

If the reset signal is asserted, what happens to the 'state' variable according to the execution table?

A It remains unchanged

B It becomes IDLE

C It becomes DONE

D It becomes WAIT

💡 Hint

Look at step 2 where reset sets the state.

Concept Snapshot

State Diagram to Verilog Translation:
- Define states as enums or parameters
- Use a state register updated on clock edge
- Compute next_state combinationally from current state and inputs
- Outputs depend on current state
- Reset initializes state
- Simulate to verify transitions

Full Transcript

This visual execution shows how to translate a state diagram into Verilog code. First, states are defined and encoded. Then a state register is created that updates on the clock or reset. Next, combinational logic decides the next state based on inputs and current state. Outputs are set based on the current state. The execution table traces each step, showing state changes and logic decisions. Key moments clarify why next_state is separate, how reset works, and output timing. The quiz tests understanding of state changes and reset behavior.