State diagram to Verilog translation - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple FSM with two states

Given the following Verilog code for a simple FSM with states IDLE and ACTIVE, what is the output out after the first clock cycle if start is 1 at reset?

Verilog

module fsm(input clk, input reset, input start, output reg out);
  typedef enum logic [1:0] {IDLE=2'b00, ACTIVE=2'b01} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= IDLE;
    else state <= next_state;
  end

  always_comb begin
    next_state = state;
    out = 0;
    case(state)
      IDLE: if (start) next_state = ACTIVE;
      ACTIVE: out = 1;
    endcase
  end
endmodule

A out = Z (high impedance)

B out = 1

C out = X (unknown)

D out = 0

💡 Hint

Combinational outputs update immediately based on the new state after the clock edge.

At reset, state is IDLE and out=0. With start=1, next_state=ACTIVE. After the first clock edge, state becomes ACTIVE, and the combinational logic sets out=1 immediately.

🧠 Conceptual

intermediate

State encoding in Verilog FSM

Which of the following is the best way to encode states in a Verilog FSM for clarity and maintainability?

A Use <code>typedef enum logic</code> with named states

B Use <code>parameter</code> constants with binary values for each state

C Use plain integers without naming states

D Use <code>localparam</code> with decimal values for states

💡 Hint

Modern Verilog supports enumerated types for better readability.

Using typedef enum logic allows named states with clear binary encoding, improving code clarity and reducing errors.

🔧 Debug

advanced

Identify the error in this FSM state transition code

What error will this Verilog FSM code produce when synthesized or simulated?

Verilog

always_ff @(posedge clk) begin
  if (reset) state <= IDLE;
  else begin
    case(state)
      IDLE: if (start) state <= ACTIVE;
      ACTIVE: state <= IDLE;
    endcase
  end
end

always_comb begin
  case(state)
    IDLE: out = 0;
    ACTIVE: out = 1;
  endcase
end

A Syntax error due to missing default case

B No error, code works correctly

C Latch inferred for 'out' signal

D Multiple drivers for 'state' signal

💡 Hint

Check if all outputs are assigned in all branches of combinational block.

The combinational block assigning 'out' does not assign 'out' in all cases, so a latch is inferred.

📝 Syntax

advanced

Correct syntax for synchronous reset in Verilog FSM

Which option shows the correct syntax for a synchronous reset in a Verilog FSM?

A always_ff @(posedge clk) begin if (reset) state <= IDLE; else state <= next_state; end

B always_ff @(posedge reset or posedge clk) begin if (reset) state <= IDLE; else state <= next_state; end

C always_ff @(posedge clk or posedge reset) begin if (reset) state <= IDLE; else state <= next_state; end

D always_ff @(negedge clk) begin if (reset) state <= IDLE; else state <= next_state; end

💡 Hint

Synchronous reset triggers only on clock edge.

Synchronous reset is checked inside the clocked block triggered only on clock edge, so reset is not in sensitivity list.

🚀 Application

expert

Number of states and output values in a Mealy FSM

A Mealy FSM has 3 states and 2 inputs. The output depends on the current state and inputs. How many unique output values can this FSM produce at maximum?

A 3

B 6

C 8

D 12

💡 Hint

Consider outputs can differ for each state-input combination.

In a Mealy FSM, output depends on state and inputs. With 3 states and 2 inputs (4 combinations), max unique outputs = 3*4 = 12.