State diagram to Verilog translation - Mini Project: Build & Apply

State diagram to Verilog translation

📖 Scenario: You are designing a simple traffic light controller using a state diagram. The traffic light has three states: Green, Yellow, and Red. Each state lasts for a fixed number of clock cycles. You want to translate this state diagram into Verilog code to control the traffic lights.

🎯 Goal: Build a Verilog module that implements the traffic light controller using a state machine. You will create the states, a counter for timing, and output signals for the lights.

📋 What You'll Learn

Create a Verilog module named traffic_light with inputs clk and reset.

Define three states: GREEN, YELLOW, and RED using localparam.

Use a register state to hold the current state.

Use a register counter to count clock cycles for timing each state.

Implement state transitions based on the counter reaching specific values.

Output signals green_light, yellow_light, and red_light that are high when the corresponding state is active.

💡 Why This Matters

🌍 Real World

Traffic light controllers are common examples of state machines used in embedded systems and digital design.

💼 Career

Understanding how to convert state diagrams into hardware description languages like Verilog is essential for FPGA and ASIC design engineers.

1

Create the module and define states

Write a Verilog module named traffic_light with inputs clk and reset. Inside the module, define three states using localparam: GREEN = 2'd0, YELLOW = 2'd1, and RED = 2'd2. Also declare a reg [1:0] state to hold the current state.

Verilog

module traffic_light(input clk, input reset);

// Define states
// Your code here

endmodule

Need a hint?

Remember to declare the module with inputs and use localparam to define states as 2-bit values.

2

Add a counter register for timing

Inside the traffic_light module, declare a 4-bit register named counter to count clock cycles for timing the states.

Verilog

module traffic_light(input clk, input reset);

    // Define states
    localparam GREEN = 2'd0;
    localparam YELLOW = 2'd1;
    localparam RED = 2'd2;

    reg [1:0] state;
    // Declare a 4-bit counter register
    // Your code here

endmodule

Need a hint?

Use reg [3:0] counter; to declare a 4-bit register for counting.

3

Implement state transitions and counter logic

Add an always @(posedge clk or posedge reset) block inside the module. On reset, set state to GREEN and counter to 0. Otherwise, increment counter. When counter reaches 4 for GREEN, move to YELLOW and reset counter. When counter reaches 2 for YELLOW, move to RED and reset counter. When counter reaches 4 for RED, move back to GREEN and reset counter.

Verilog

module traffic_light(input clk, input reset);

    // Define states
    localparam GREEN = 2'd0;
    localparam YELLOW = 2'd1;
    localparam RED = 2'd2;

    reg [1:0] state;
    reg [3:0] counter;

    always @(posedge clk or posedge reset) begin
        // Your code here
    end

endmodule

Need a hint?

Use a synchronous reset and a case statement to handle state transitions and counter resets.

4

Add output signals for the traffic lights

Declare output registers green_light, yellow_light, and red_light. Inside an always @(*) block, set these outputs to 1 when the state matches their color, otherwise 0. Finally, add these outputs to the module's port list.

Verilog

module traffic_light(input clk, input reset, output reg green_light, output reg yellow_light, output reg red_light);

    // Define states
    localparam GREEN = 2'd0;
    localparam YELLOW = 2'd1;
    localparam RED = 2'd2;

    reg [1:0] state;
    reg [3:0] counter;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= GREEN;
            counter <= 0;
        end else begin
            counter <= counter + 1;
            case (state)
                GREEN: if (counter == 4) begin
                    state <= YELLOW;
                    counter <= 0;
                end
                YELLOW: if (counter == 2) begin
                    state <= RED;
                    counter <= 0;
                end
                RED: if (counter == 4) begin
                    state <= GREEN;
                    counter <= 0;
                end
            endcase
        end
    end

    always @(*) begin
        // Your code here
    end

endmodule

Need a hint?

Use a combinational always @(*) block to set the output signals based on the current state.