State diagram to Verilog translation - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state register.

Verilog

reg [1:0] [1] ;

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Aoutput

Binput

Cstate

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using input or output instead of state for the register name.

The state register holds the current state of the FSM.

2fill in blank

medium

Complete the code to define the next state logic.

Verilog

always @(*) begin
  case (state)
    2'b00: next_state = [1];
    default: next_state = 2'b00;
  endcase
end

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A2'b01

B2'b11

C2'b10

D2'b00

Attempts:

3 left

💡 Hint

Common Mistakes

Choosing the current state as next state incorrectly.

The next state after 2'b00 is 2'b01 as per the state diagram.

3fill in blank

hard

Fix the error in the state update block.

Verilog

always @(posedge clk or posedge reset) begin
  if ([1]) state <= 2'b00;
  else state <= next_state;
end

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Anext_state

Breset

Cclk

Dstate

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk instead of reset in the if condition.

The reset signal asynchronously resets the state to 2'b00.

4fill in blank

hard

Fill both blanks to complete the output logic based on state.

Verilog

always @(*) begin
  case ([1])
    2'b01: output_signal = [2];
    default: output_signal = 1'b0;
  endcase
end

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Astate

Bnext_state

C1'b1

D1'b0

Attempts:

3 left

💡 Hint

Common Mistakes

Using next_state instead of state for output logic.

The output depends on the current state. When state is 2'b01, output_signal is 1.

5fill in blank

hard

Fill all three blanks to complete the full FSM module skeleton.

Verilog

module fsm(clk, reset, output_signal);
  input [1];
  input [2];
  output reg [3];

  reg [1:0] state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= 2'b00;
    else state <= next_state;
  end

  always @(*) begin
    case (state)
      2'b00: next_state = 2'b01;
      2'b01: next_state = 2'b10;
      default: next_state = 2'b00;
    endcase
  end

  always @(*) begin
    case (state)
      2'b01: output_signal = 1'b1;
      default: output_signal = 1'b0;
    endcase
  end
endmodule

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Aclk

Breset

Coutput_signal

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing input and output declarations.

The module inputs are clk and reset, and output is output_signal.