Shift register (SIPO, PISO, SISO) in Verilog - Step-by-Step Execution

Concept Flow - Shift register (SIPO, PISO, SISO)

Input Data

↓

Shift Register

↓

SISO

↓

Serial

Data enters the shift register and moves through it. SISO shifts data serially in and out. SIPO converts serial input to parallel output. PISO loads parallel data and shifts it out serially.

Execution Sample

Verilog

module siso_shift_register(input clk, input serial_in, output reg serial_out);
  reg [3:0] shift_reg = 4'b0000;
  always @(posedge clk) begin
    serial_out <= shift_reg[3];
    shift_reg <= {shift_reg[2:0], serial_in};
  end
endmodule

A 4-bit SISO shift register shifts serial input in and outputs serial data.

Execution Table

Clock Cycle	shift_reg (bits)	serial_in	serial_out	Action
0	0000	0	0	Initial state
1	0001	1	0	Shift in 1: shift_reg=0001, output=0
2	0010	0	0	Shift in 0: shift_reg=0010, output=0
3	0101	1	0	Shift in 1: shift_reg=0101, output=0
4	1011	1	0	Shift in 1: shift_reg=1011, output=0
5	0110	0	1	Shift in 0: shift_reg=0110, output=1

💡 After 5 clock cycles, shift_reg contains last 4 serial inputs, serial_out is MSB shifted out.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
shift_reg	0000	0001	0010	0101	1011	0110
serial_in	0	1	0	1	1	0
serial_out	0	0	0	0	0	1

Key Moments - 3 Insights

Why does serial_out show the previous MSB and not the new input immediately?

Because serial_out is assigned from shift_reg[3] before the new input shifts in, it outputs the MSB from the previous cycle as shown in execution_table rows 1-5.

How does the shift_reg update each clock cycle?

At each clock, shift_reg shifts left by one bit and inserts serial_in at LSB, as seen in the 'Action' column of execution_table.

What happens if serial_in stays constant?

shift_reg will fill with that constant bit over cycles, eventually all bits become that value, shown by tracking shift_reg in variable_tracker.

Visual Quiz - 3 Questions

Look at the execution_table at Clock Cycle 3, what is the value of shift_reg?

A 1011

B 0010

C 0101

D 0001

💡 Hint

Check the 'shift_reg (bits)' column at Clock Cycle 3 in execution_table.

At which clock cycle does serial_out first become 1?

A 3

B 5

C 2

D 4

💡 Hint

Look at the 'serial_out' column in execution_table and find when it changes to 1.

If serial_in was always 1, what would shift_reg be after 4 cycles?

A 1111

B 0000

C 1000

D 0111

💡 Hint

Refer to variable_tracker and imagine serial_in as 1 each cycle shifting into shift_reg.

Concept Snapshot

Shift register moves bits through flip-flops on clock edges.
SISO: Serial input, serial output.
SIPO: Serial input, parallel output.
PISO: Parallel input, serial output.
Data shifts one bit per clock cycle.
Outputs depend on register content and type.

Full Transcript

This visual trace shows a 4-bit SISO shift register in Verilog. The shift register starts empty. Each clock cycle, it shifts bits left and inserts the serial input at the right. The serial output is the leftmost bit shifted out. The execution table tracks the register bits, input, and output each cycle. Key moments clarify why output lags input and how bits move. The quiz tests understanding of register state and output timing. The snapshot summarizes shift register types and behavior.