Shift register (SIPO, PISO, SISO) in Verilog - Step-by-Step Execution

Concept Flow - Shift register (SIPO, PISO, SISO)

Input Data

↓

Shift Register

↓

SISO

↓

Serial

Data enters the shift register and moves through it. SISO shifts data serially in and out. SIPO converts serial input to parallel output. PISO loads parallel data and shifts it out serially.

Execution Sample

Verilog

module siso_shift_register(input clk, input serial_in, output reg serial_out);
  reg [3:0] shift_reg = 4'b0000;
  always @(posedge clk) begin
    serial_out <= shift_reg[3];
    shift_reg <= {shift_reg[2:0], serial_in};
  end
endmodule

A 4-bit SISO shift register shifts serial input in and outputs serial data.

Execution Table

Clock Cycle	shift_reg (bits)	serial_in	serial_out	Action
0	0000	0	0	Initial state
1	0001	1	0	Shift in 1: shift_reg=0001, output=0
2	0010	0	0	Shift in 0: shift_reg=0010, output=0
3	0101	1	0	Shift in 1: shift_reg=0101, output=0
4	1011	1	0	Shift in 1: shift_reg=1011, output=0
5	0110	0	1	Shift in 0: shift_reg=0110, output=1

💡 After 5 clock cycles, shift_reg contains last 4 serial inputs, serial_out is MSB shifted out.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
shift_reg	0000	0001	0010	0101	1011	0110
serial_in	0	1	0	1	1	0
serial_out	0	0	0	0	0	1

Key Moments - 3 Insights

Why does serial_out show the previous MSB and not the new input immediately?

Because serial_out is assigned from shift_reg[3] before the new input shifts in, it outputs the MSB from the previous cycle as shown in execution_table rows 1-5.

How does the shift_reg update each clock cycle?

At each clock, shift_reg shifts left by one bit and inserts serial_in at LSB, as seen in the 'Action' column of execution_table.

What happens if serial_in stays constant?

shift_reg will fill with that constant bit over cycles, eventually all bits become that value, shown by tracking shift_reg in variable_tracker.

Visual Quiz - 3 Questions

Look at the execution_table at Clock Cycle 3, what is the value of shift_reg?

A 1011

B 0010

C 0101

D 0001

💡 Hint

Check the 'shift_reg (bits)' column at Clock Cycle 3 in execution_table.

At which clock cycle does serial_out first become 1?

A 3

B 5

C 2

D 4

💡 Hint

Look at the 'serial_out' column in execution_table and find when it changes to 1.

If serial_in was always 1, what would shift_reg be after 4 cycles?

A 1111

B 0000

C 1000

D 0111

💡 Hint

Refer to variable_tracker and imagine serial_in as 1 each cycle shifting into shift_reg.

Concept Snapshot

Shift register moves bits through flip-flops on clock edges.
SISO: Serial input, serial output.
SIPO: Serial input, parallel output.
PISO: Parallel input, serial output.
Data shifts one bit per clock cycle.
Outputs depend on register content and type.

Full Transcript

This visual trace shows a 4-bit SISO shift register in Verilog. The shift register starts empty. Each clock cycle, it shifts bits left and inserts the serial input at the right. The serial output is the leftmost bit shifted out. The execution table tracks the register bits, input, and output each cycle. Key moments clarify why output lags input and how bits move. The quiz tests understanding of register state and output timing. The snapshot summarizes shift register types and behavior.

Practice

1. Which type of shift register converts serial input data into parallel output data?

easy

A. SISO (Serial-In Serial-Out)

B. PISO (Parallel-In Serial-Out)

C. PIPO (Parallel-In Parallel-Out)

D. SIPO (Serial-In Parallel-Out)

Solution

1. Step 1: Understand shift register types

   SIPO means data enters serially and exits in parallel form.

2. Step 2: Match the description

   The question asks for serial input to parallel output, which matches SIPO.

3. Final Answer:

   SIPO (Serial-In Parallel-Out) -> Option D

4. Quick Check:

   Serial input to parallel output = SIPO [OK]

Hint: Remember SIPO = Serial input, Parallel output [OK]

Common Mistakes:

• Confusing PISO with SIPO
• Thinking SISO converts to parallel output
• Mixing up input and output directions

2. Which of the following is the correct Verilog port declaration for a 4-bit PISO shift register input?

easy

A. input [3:0] parallel_in

B. output [3:0] parallel_in

C. input serial_in

D. output serial_out

Solution

1. Step 1: Identify PISO input type

   PISO shift register takes parallel input, so input must be a bus (multiple bits).

2. Step 2: Check port declaration syntax

   input [3:0] parallel_in correctly declares a 4-bit input bus.

3. Final Answer:

   input [3:0] parallel_in -> Option A

4. Quick Check:

   Parallel input uses input [3:0] [OK]

Hint: Parallel inputs use bus syntax: input [n:0] name [OK]

Common Mistakes:

• Using output instead of input for inputs
• Declaring parallel input as single bit
• Confusing serial and parallel port directions

3. Given this Verilog code snippet for a 4-bit SISO shift register, what is the value of q after 3 clock cycles if d inputs are 1, 0, 1 respectively?

reg [3:0] q;
always @(posedge clk) begin
  q <= {q[2:0], d};
end

medium

A. 4'b0101

B. 4'b0011

C. 4'b1010

D. 4'b1001

Solution

1. Step 1: Understand shifting operation

   Each clock, bits shift left and new bit d enters at LSB (rightmost).

2. Step 2: Trace each clock cycle

   Initial q=0000 (assumed).
   Cycle 1: q=0000 -> shift left + d=1 -> 0001
   Cycle 2: q=0001 -> shift left + d=0 -> 0010
   Cycle 3: q=0010 -> shift left + d=1 -> 0101

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   Shift left + input d = 0101 after 3 cycles [OK]

Hint: Shift left and add new bit at right each clock [OK]

Common Mistakes:

• Assuming shift right instead of left
• Not updating q each cycle
• Mixing bit order in concatenation

4. Identify the error in this Verilog code for a 4-bit PISO shift register:

module piso_shift(
  input clk,
  input [3:0] parallel_in,
  input load,
  output reg serial_out
);
  reg [3:0] shift_reg;
  always @(posedge clk) begin
    if (load)
      shift_reg <= parallel_in;
    else
      shift_reg <= shift_reg >> 1;
    serial_out <= shift_reg[0];
  end
endmodule

medium

A. Shift direction is wrong; should shift left instead of right

B. serial_out should output shift_reg[3], not shift_reg[0]

C. serial_out should be assigned before shifting

D. load signal should be asynchronous

Solution

1. Step 1: Understand PISO operation

   PISO outputs bits serially starting from the most significant bit (MSB), which is shift_reg[3] here.

2. Step 2: Check serial_out assignment

   Code assigns serial_out = shift_reg[0], which is the least significant bit (LSB), incorrect for PISO.

3. Final Answer:

   serial_out should output shift_reg[3], not shift_reg[0] -> Option B

4. Quick Check:

   PISO outputs MSB first = shift_reg[3] [OK]

Hint: PISO outputs MSB first, so serial_out = shift_reg[3] [OK]

Common Mistakes:

• Assigning serial_out to LSB instead of MSB
• Confusing shift direction for PISO
• Thinking load must be asynchronous

5. You want to design a shift register that takes 8-bit parallel data and outputs it serially one bit per clock cycle. Which type of shift register should you use and how would you implement the output logic in Verilog?

hard

A. Use a PIPO shift register; input parallel data and output parallel data

B. Use a SIPO shift register; input serial data and output parallel bits

C. Use a PISO shift register; load 8-bit data and shift out MSB serially each clock

D. Use a SISO shift register; input serial data and output serial data

Solution

1. Step 1: Identify required functionality

   The design needs to convert parallel input to serial output, which matches PISO behavior.

2. Step 2: Describe implementation

   Load 8-bit parallel data into a register on load signal, then shift right each clock cycle outputting MSB (or LSB depending on design) as serial output.

3. Final Answer:

   Use a PISO shift register; load 8-bit data and shift out MSB serially each clock -> Option C

4. Quick Check:

   Parallel to serial = PISO shift register [OK]

Hint: Parallel input to serial output means use PISO shift register [OK]

Common Mistakes:

• Choosing SIPO instead of PISO
• Confusing serial input with parallel input
• Using SISO which only shifts serial data