Shift register (SIPO, PISO, SISO) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit shift register.

Verilog

reg [3:0] [1] ;

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Ashift_reg

Bdata_out

Cinput_data

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using signal names like clk or input_data as register name.

The shift register is declared as a 4-bit register named shift_reg.

2fill in blank

medium

Complete the code to shift data left by one bit on the rising edge of clock.

Verilog

always @(posedge clk) begin
    [1] <= {shift_reg[2:0], serial_in};
end

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Aserial_out

Bshift_reg

Cdata_in

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning to serial_out or clk inside always block.

The shift register shift_reg is updated by shifting left and inserting serial_in at LSB.

3fill in blank

hard

Fix the error in the code to correctly output the serial data from the shift register.

Verilog

assign serial_out = [1][3];

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Adata_in

Bclk

Cshift_reg

Dserial_in

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning output from serial_in or clock signals.

The output serial_out should be assigned from the MSB of the shift register shift_reg.

4fill in blank

hard

Fill both blanks to complete the parallel load logic for a PISO shift register.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset) begin
        shift_reg <= 4'b0000;
    end else if (load) begin
        shift_reg <= [1];
    end else begin
        shift_reg <= {shift_reg[2:0], [2];
    end
end

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Aparallel_in

Bserial_out

Cserial_in

Dload

Attempts:

3 left

💡 Hint

Common Mistakes

Using serial_out instead of serial_in for shifting.

On load, the shift register takes the parallel input parallel_in. Otherwise, it shifts left inserting serial_in.

5fill in blank

hard

Fill all three blanks to complete a SISO shift register that shifts right and outputs the LSB.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset) begin
        shift_reg <= 4'b0000;
    end else begin
        shift_reg <= { [1], shift_reg[3:1] };
    end
end

assign [3] = shift_reg[[2]];

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Aserial_in

B0

Dserial_out

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing MSB and LSB positions in shifting and output.

The shift register shifts right by inserting serial_in at MSB. The output is the LSB shift_reg[0]. A wire serial_out is assigned to output.