Shift register (SIPO, PISO, SISO) in Verilog - Mini Project: Build & Apply

Shift register (SIPO, PISO, SISO)

📋 What You'll Learn

💡 Why This Matters

🌍 Real World

Shift registers are used in digital electronics to convert data formats, delay signals, and build memory elements.

💼 Career

Understanding shift registers is essential for hardware design engineers working with FPGAs, ASICs, and embedded systems.

1

Create a 4-bit SIPO shift register module

Write a Verilog module called SIPO with inputs clk, reset, and serial_in. Create a 4-bit output parallel_out. Inside, use a 4-bit register called shift_reg. On the rising edge of clk, if reset is high, clear shift_reg to 0. Otherwise, shift shift_reg left by 1 and put serial_in into the least significant bit. Assign parallel_out to shift_reg.

Verilog

// Your code here

Need a hint?

Think of shift_reg as a row of 4 boxes. Each clock tick, move all bits one box to the left and put the new bit in the rightmost box.

2

Create a 4-bit PISO shift register module

Add a new Verilog module called PISO with inputs clk, reset, load, and 4-bit parallel_in. Create a 1-bit output serial_out. Use a 4-bit register shift_reg. On the rising edge of clk, if reset is high, clear shift_reg. Else if load is high, load parallel_in into shift_reg. Otherwise, shift shift_reg right by 1. Assign serial_out to the least significant bit of shift_reg.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

// Your code here

Need a hint?

Imagine loading 4 beads at once, then pushing them out one by one from the right side.

3

Create a 4-bit SISO shift register module

Add a Verilog module called SISO with inputs clk, reset, and serial_in. Create a 1-bit output serial_out. Use a 4-bit register shift_reg. On the rising edge of clk, if reset is high, clear shift_reg. Otherwise, shift shift_reg left by 1 and put serial_in into the least significant bit. Assign serial_out to the most significant bit of shift_reg.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

module PISO(input clk, input reset, input load, input [3:0] parallel_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else if (load) begin
            shift_reg <= parallel_in;
        end else begin
            shift_reg <= {1'b0, shift_reg[3:1]};
        end
    end
    always @(*) begin
        serial_out = shift_reg[0];
    end
endmodule

// Your code here

Need a hint?

This is like SIPO but you only watch the leftmost bit as output, moving bits one by one.

4

Test and display outputs of all shift registers

Write a testbench module called test_shift_registers. Declare reg clk, reset, serial_in, load, and [3:0] parallel_in. Declare wires [3:0] parallel_out and serial_out_piso, serial_out_siso. Instantiate SIPO, PISO, and SISO modules with these signals. Initialize clk to 0 and toggle it every 5 time units. Apply a reset pulse at start. Load parallel_in with 4'b1010 and set load high for one clock cycle. Feed serial_in with bits 1,0,1,1 on consecutive clock cycles. Use $display to print parallel_out, serial_out_piso, and serial_out_siso at each clock rising edge.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

module PISO(input clk, input reset, input load, input [3:0] parallel_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else if (load) begin
            shift_reg <= parallel_in;
        end else begin
            shift_reg <= {1'b0, shift_reg[3:1]};
        end
    end
    always @(*) begin
        serial_out = shift_reg[0];
    end
endmodule

module SISO(input clk, input reset, input serial_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        serial_out = shift_reg[3];
    end
endmodule

// Your code here

Need a hint?

Use a clock that toggles every 5 time units. Reset first, then load parallel data into PISO. Feed serial bits to SIPO and SISO. Print outputs at each clock rising edge.