Shift register (SIPO, PISO, SISO) in Verilog - Mini Project: Build & Apply

Shift register (SIPO, PISO, SISO)

📋 What You'll Learn

💡 Why This Matters

🌍 Real World

Shift registers are used in digital electronics to convert data formats, delay signals, and build memory elements.

💼 Career

Understanding shift registers is essential for hardware design engineers working with FPGAs, ASICs, and embedded systems.

1

Create a 4-bit SIPO shift register module

Write a Verilog module called SIPO with inputs clk, reset, and serial_in. Create a 4-bit output parallel_out. Inside, use a 4-bit register called shift_reg. On the rising edge of clk, if reset is high, clear shift_reg to 0. Otherwise, shift shift_reg left by 1 and put serial_in into the least significant bit. Assign parallel_out to shift_reg.

Verilog

// Your code here

Hint

Think of shift_reg as a row of 4 boxes. Each clock tick, move all bits one box to the left and put the new bit in the rightmost box.

2

Create a 4-bit PISO shift register module

Add a new Verilog module called PISO with inputs clk, reset, load, and 4-bit parallel_in. Create a 1-bit output serial_out. Use a 4-bit register shift_reg. On the rising edge of clk, if reset is high, clear shift_reg. Else if load is high, load parallel_in into shift_reg. Otherwise, shift shift_reg right by 1. Assign serial_out to the least significant bit of shift_reg.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

// Your code here

Hint

Imagine loading 4 beads at once, then pushing them out one by one from the right side.

3

Create a 4-bit SISO shift register module

Add a Verilog module called SISO with inputs clk, reset, and serial_in. Create a 1-bit output serial_out. Use a 4-bit register shift_reg. On the rising edge of clk, if reset is high, clear shift_reg. Otherwise, shift shift_reg left by 1 and put serial_in into the least significant bit. Assign serial_out to the most significant bit of shift_reg.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

module PISO(input clk, input reset, input load, input [3:0] parallel_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else if (load) begin
            shift_reg <= parallel_in;
        end else begin
            shift_reg <= {1'b0, shift_reg[3:1]};
        end
    end
    always @(*) begin
        serial_out = shift_reg[0];
    end
endmodule

// Your code here

Hint

This is like SIPO but you only watch the leftmost bit as output, moving bits one by one.

4

Test and display outputs of all shift registers

Write a testbench module called test_shift_registers. Declare reg clk, reset, serial_in, load, and [3:0] parallel_in. Declare wires [3:0] parallel_out and serial_out_piso, serial_out_siso. Instantiate SIPO, PISO, and SISO modules with these signals. Initialize clk to 0 and toggle it every 5 time units. Apply a reset pulse at start. Load parallel_in with 4'b1010 and set load high for one clock cycle. Feed serial_in with bits 1,0,1,1 on consecutive clock cycles. Use $display to print parallel_out, serial_out_piso, and serial_out_siso at each clock rising edge.

Verilog

module SIPO(input clk, input reset, input serial_in, output reg [3:0] parallel_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

module PISO(input clk, input reset, input load, input [3:0] parallel_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else if (load) begin
            shift_reg <= parallel_in;
        end else begin
            shift_reg <= {1'b0, shift_reg[3:1]};
        end
    end
    always @(*) begin
        serial_out = shift_reg[0];
    end
endmodule

module SISO(input clk, input reset, input serial_in, output reg serial_out);
    reg [3:0] shift_reg;
    always @(posedge clk) begin
        if (reset) begin
            shift_reg <= 4'b0000;
        end else begin
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
    always @(*) begin
        serial_out = shift_reg[3];
    end
endmodule

// Your code here

Hint

Use a clock that toggles every 5 time units. Reset first, then load parallel data into PISO. Feed serial bits to SIPO and SISO. Print outputs at each clock rising edge.

Practice

1. Which type of shift register converts serial input data into parallel output data?

easy

A. SISO (Serial-In Serial-Out)

B. PISO (Parallel-In Serial-Out)

C. PIPO (Parallel-In Parallel-Out)

D. SIPO (Serial-In Parallel-Out)

Solution

1. Step 1: Understand shift register types

   SIPO means data enters serially and exits in parallel form.

2. Step 2: Match the description

   The question asks for serial input to parallel output, which matches SIPO.

3. Final Answer:

   SIPO (Serial-In Parallel-Out) -> Option D

4. Quick Check:

   Serial input to parallel output = SIPO [OK]

Hint: Remember SIPO = Serial input, Parallel output [OK]

Common Mistakes:

• Confusing PISO with SIPO
• Thinking SISO converts to parallel output
• Mixing up input and output directions

2. Which of the following is the correct Verilog port declaration for a 4-bit PISO shift register input?

easy

A. input [3:0] parallel_in

B. output [3:0] parallel_in

C. input serial_in

D. output serial_out

Solution

1. Step 1: Identify PISO input type

   PISO shift register takes parallel input, so input must be a bus (multiple bits).

2. Step 2: Check port declaration syntax

   input [3:0] parallel_in correctly declares a 4-bit input bus.

3. Final Answer:

   input [3:0] parallel_in -> Option A

4. Quick Check:

   Parallel input uses input [3:0] [OK]

Hint: Parallel inputs use bus syntax: input [n:0] name [OK]

Common Mistakes:

• Using output instead of input for inputs
• Declaring parallel input as single bit
• Confusing serial and parallel port directions

3. Given this Verilog code snippet for a 4-bit SISO shift register, what is the value of q after 3 clock cycles if d inputs are 1, 0, 1 respectively?

reg [3:0] q;
always @(posedge clk) begin
  q <= {q[2:0], d};
end

medium

A. 4'b0101

B. 4'b0011

C. 4'b1010

D. 4'b1001

Solution

1. Step 1: Understand shifting operation

   Each clock, bits shift left and new bit d enters at LSB (rightmost).

2. Step 2: Trace each clock cycle

   Initial q=0000 (assumed).
   Cycle 1: q=0000 -> shift left + d=1 -> 0001
   Cycle 2: q=0001 -> shift left + d=0 -> 0010
   Cycle 3: q=0010 -> shift left + d=1 -> 0101

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   Shift left + input d = 0101 after 3 cycles [OK]

Hint: Shift left and add new bit at right each clock [OK]

Common Mistakes:

• Assuming shift right instead of left
• Not updating q each cycle
• Mixing bit order in concatenation

4. Identify the error in this Verilog code for a 4-bit PISO shift register:

module piso_shift(
  input clk,
  input [3:0] parallel_in,
  input load,
  output reg serial_out
);
  reg [3:0] shift_reg;
  always @(posedge clk) begin
    if (load)
      shift_reg <= parallel_in;
    else
      shift_reg <= shift_reg >> 1;
    serial_out <= shift_reg[0];
  end
endmodule

medium

A. Shift direction is wrong; should shift left instead of right

B. serial_out should output shift_reg[3], not shift_reg[0]

C. serial_out should be assigned before shifting

D. load signal should be asynchronous

Solution

1. Step 1: Understand PISO operation

   PISO outputs bits serially starting from the most significant bit (MSB), which is shift_reg[3] here.

2. Step 2: Check serial_out assignment

   Code assigns serial_out = shift_reg[0], which is the least significant bit (LSB), incorrect for PISO.

3. Final Answer:

   serial_out should output shift_reg[3], not shift_reg[0] -> Option B

4. Quick Check:

   PISO outputs MSB first = shift_reg[3] [OK]

Hint: PISO outputs MSB first, so serial_out = shift_reg[3] [OK]

Common Mistakes:

• Assigning serial_out to LSB instead of MSB
• Confusing shift direction for PISO
• Thinking load must be asynchronous

5. You want to design a shift register that takes 8-bit parallel data and outputs it serially one bit per clock cycle. Which type of shift register should you use and how would you implement the output logic in Verilog?

hard

A. Use a PIPO shift register; input parallel data and output parallel data

B. Use a SIPO shift register; input serial data and output parallel bits

C. Use a PISO shift register; load 8-bit data and shift out MSB serially each clock

D. Use a SISO shift register; input serial data and output serial data

Solution

1. Step 1: Identify required functionality

   The design needs to convert parallel input to serial output, which matches PISO behavior.

2. Step 2: Describe implementation

   Load 8-bit parallel data into a register on load signal, then shift right each clock cycle outputting MSB (or LSB depending on design) as serial output.

3. Final Answer:

   Use a PISO shift register; load 8-bit data and shift out MSB serially each clock -> Option C

4. Quick Check:

   Parallel to serial = PISO shift register [OK]

Hint: Parallel input to serial output means use PISO shift register [OK]

Common Mistakes:

• Choosing SIPO instead of PISO
• Confusing serial input with parallel input
• Using SISO which only shifts serial data