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Verilogprogramming~20 mins

Shift register (SIPO, PISO, SISO) in Verilog - Practice Problems & Coding Challenges

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Challenge - 5 Problems
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❓ Predict Output
intermediate
2:00remaining
Output of a 4-bit SIPO shift register
What is the output of the 4-bit SIPO shift register after 4 clock cycles if the serial input is 1, 0, 1, 1 respectively?

Assume the register is initially cleared (all zeros).
Verilog
module sipo(clk, serial_in, parallel_out);
  input clk, serial_in;
  output reg [3:0] parallel_out;

  always @(posedge clk) begin
    parallel_out <= {parallel_out[2:0], serial_in};
  end
endmodule
Aparallel_out = 4'b1101
Bparallel_out = 4'b1011
Cparallel_out = 4'b0111
Dparallel_out = 4'b1001
Attempts:
2 left
💡 Hint
Think about how bits shift in from the right and older bits move left.
❓ Predict Output
intermediate
2:00remaining
Output of a 4-bit PISO shift register
Given a 4-bit PISO shift register loaded with 4'b1101, what is the serial output after 4 clock cycles if no new parallel load occurs?

Assume the serial output is the least significant bit shifted out.
Verilog
module piso(clk, load, parallel_in, serial_out);
  input clk, load;
  input [3:0] parallel_in;
  output reg serial_out;
  reg [3:0] shift_reg;

  always @(posedge clk) begin
    if (load) shift_reg <= parallel_in;
    else begin
      serial_out <= shift_reg[0];
      shift_reg <= shift_reg >> 1;
    end
  end
endmodule
ASerial output sequence: 1, 0, 1, 1
BSerial output sequence: 1, 1, 0, 1
CSerial output sequence: 1, 0, 0, 1
DSerial output sequence: 0, 1, 1, 0
Attempts:
2 left
💡 Hint
Look at the least significant bit shifting out each cycle.
🔧 Debug
advanced
2:00remaining
Identify the error in this SISO shift register code
This SISO shift register code is intended to shift a single bit serially on each clock. What error will it cause when synthesized or simulated?
Verilog
module siso(clk, serial_in, serial_out);
  input clk, serial_in;
  output reg serial_out;

  always @(posedge clk) begin
    serial_out <= serial_in;
    serial_in <= serial_out;
  end
endmodule
ASynthesis error: Missing reset signal
BNo error, works as intended
CRuntime error: serial_out never changes
DSyntax error: Cannot assign to input 'serial_in'
Attempts:
2 left
💡 Hint
Inputs cannot be assigned values inside the module.
📝 Syntax
advanced
2:00remaining
Syntax error in PISO shift register code
Which option contains the correct syntax to shift right and output the least significant bit in a PISO register on positive clock edge?
Aalways @(posedge clk) begin serial_out = shift_reg[0]; shift_reg = shift_reg >> 1; end
Balways @(posedge clk) begin serial_out <= shift_reg[0]; shift_reg <= shift_reg << 1; end
Calways @(posedge clk) begin serial_out <= shift_reg[0]; shift_reg <= shift_reg >> 1; end
Dalways @(posedge clk) begin serial_out <= shift_reg[3]; shift_reg <= shift_reg >> 1; end
Attempts:
2 left
💡 Hint
Remember to use non-blocking assignments for sequential logic and shift in the correct direction.
🚀 Application
expert
3:00remaining
Determine the final parallel output of a 4-bit SIPO after mixed inputs
A 4-bit SIPO shift register starts cleared (0000). The serial input bits over 5 clock cycles are: 1, 1, 0, 1, 0.

What is the parallel output after the 5th clock cycle?

Note: The register shifts left each clock, inserting the new bit at the rightmost position.
Verilog
module sipo(clk, serial_in, parallel_out);
  input clk, serial_in;
  output reg [3:0] parallel_out;

  always @(posedge clk) begin
    parallel_out <= {parallel_out[2:0], serial_in};
  end
endmodule
A4'b1010
B4'b1101
C4'b0110
D4'b0101
Attempts:
2 left
💡 Hint
Track the bits shifting in one by one, oldest bit moves left out of the register.