Register (multi-bit flip-flop) in Verilog - Step-by-Step Execution

Concept Flow - Register (multi-bit flip-flop)

Start

↓

Wait for clock edge

↓

On rising edge?

No→Wait

Yes↓

Load input data into register

↓

Hold data stable

↓

Output register value

↓

Repeat on next clock edge

This flow shows how a multi-bit register waits for a clock signal, then loads and holds data on each rising clock edge.

Execution Sample

Verilog

module register(clk, reset, d, q);
  input clk, reset;
  input [3:0] d;
  output reg [3:0] q;

  always @(posedge clk or posedge reset) begin
    if (reset) q <= 4'b0000;
    else q <= d;
  end
endmodule

This Verilog code defines a 4-bit register that loads input d into q on the rising clock edge or resets q to zero.

Execution Table

Step	clk	reset	d	Condition	Action	q (register output)
1	0	1	4'b1010	reset=1?	Yes, q <= 0000	0000
2	1 (rising edge)	0	4'b1010	reset=0?	Load d into q	1010
3	0	0	4'b1100	No clock edge	Hold q	1010
4	1 (rising edge)	0	4'b1100	reset=0?	Load d into q	1100
5	0	0	4'b1111	No clock edge	Hold q	1100
6	1 (rising edge)	0	4'b1111	reset=0?	Load d into q	1111
7	1 (rising edge)	1	4'b0001	reset=1?	Reset q to 0000	0000

💡 Simulation ends after reset is asserted again, register output reset to zero.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7
clk	0	0	1	0	1	0	1	1
reset	0	1	0	0	0	0	0	1
d	0000	1010	1010	1100	1100	1111	1111	0001
q	0000	0000	1010	1010	1100	1100	1111	0000

Key Moments - 3 Insights

Why does the register output q change only on the rising edge of clk?

Because the always block triggers only on posedge clk or posedge reset, so q updates only when clk rises or reset is active, as shown in steps 2, 4, 6, and 7.

What happens to q when reset is high, even if clk is not rising?

When reset is high, q is immediately set to zero regardless of clk, as seen in step 1 and step 7 in the execution_table.

Why does q hold its value when clk is low or no rising edge occurs?

Because the always block does not trigger without a rising edge on clk or reset, so q keeps its previous value, shown in steps 3 and 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 4?

A 1100

B 1010

C 0000

D 1111

💡 Hint

Check the 'q' column in row for step 4 in execution_table.

At which step does the reset signal cause q to become 0000?

A Step 4

B Step 1

C Step 2

D Step 6

💡 Hint

Look for steps where reset=1 and q is set to 0000 in execution_table.

If the reset signal stayed low, what would q be after step 7?

A 0000

B 1010

C 1111

D 1100

💡 Hint

Refer to variable_tracker for q values and consider reset effect at step 7.

Concept Snapshot

Register (multi-bit flip-flop) in Verilog:
- Use always @(posedge clk or posedge reset) block
- On reset=1, set q to zero
- On rising clk, load input d into q
- q holds value between clock edges
- Useful for storing multi-bit data synchronously

Full Transcript

This visual execution trace shows a 4-bit register in Verilog. The register waits for a rising clock edge or a reset signal. When reset is high, the register output q is set to zero immediately. On each rising clock edge, if reset is low, the input data d is loaded into q. Between clock edges, q holds its value stable. The execution table traces each step with clk, reset, d, and q values. The variable tracker shows how signals change over time. Key moments clarify why q updates only on clock edges or reset, and why it holds value otherwise. The quiz questions test understanding of q's value changes and reset behavior. This helps beginners see how a multi-bit flip-flop register works step-by-step.

Practice

1.

What is the main purpose of a multi-bit register in Verilog?

easy

A. To store multiple bits of data and update them on clock edges

B. To perform arithmetic operations on data

C. To generate clock signals

D. To convert analog signals to digital

Solution

1. Step 1: Understand the function of a register

   A register is used to hold data bits temporarily in digital circuits.

2. Step 2: Recognize clock edge behavior

   Registers update their stored data only on clock edges, making them synchronous storage elements.

3. Final Answer:

   To store multiple bits of data and update them on clock edges -> Option A

4. Quick Check:

   Register = multi-bit storage updated on clock edges [OK]

Hint: Registers store bits and update only on clock edges [OK]

Common Mistakes:

• Confusing registers with combinational logic
• Thinking registers generate clocks
• Assuming registers perform arithmetic

2.

Which of the following is the correct way to declare an 8-bit register in Verilog?

?

easy

A. reg [7:0] my_reg;

B. reg my_reg[7:0];

C. register [8] my_reg;

D. reg my_reg : 8;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with 'reg' keyword followed by bit range in square brackets before the name.

2. Step 2: Check each option

   reg [7:0] my_reg; uses correct syntax: 'reg [7:0] my_reg;'. Others have syntax errors or wrong keywords.

3. Final Answer:

   reg [7:0] my_reg; -> Option A

4. Quick Check:

   Correct reg declaration = reg [7:0] name; [OK]

Hint: Use reg [MSB:LSB] name; to declare multi-bit registers [OK]

Common Mistakes:

• Placing bit range after variable name
• Using 'register' keyword instead of 'reg'
• Using colon instead of square brackets

3.

Given the following Verilog code, what will be the value of reg_out after the positive edge of clk if reset is 0 and data_in is 8'b10101010?

module reg_example(input clk, input reset, input [7:0] data_in, output reg [7:0] reg_out);
  always @(posedge clk or posedge reset) begin
    if (reset)
      reg_out <= 8'b00000000;
    else
      reg_out <= data_in;
  end
endmodule

medium

A. 8'b00000000

B. 8'b10101010

C. 8'b11111111

D. No change in reg_out

Solution

1. Step 1: Analyze the always block sensitivity

   The block triggers on positive edge of clk or reset. If reset is high, reg_out resets to zero.

2. Step 2: Check conditions given

   Reset is 0, so reg_out will be assigned data_in value on clk rising edge, which is 8'b10101010.

3. Final Answer:

   8'b10101010 -> Option B

4. Quick Check:

   Reset=0, reg_out = data_in = 10101010 [OK]

Hint: If reset=0, reg_out updates to data_in on clk edge [OK]

Common Mistakes:

• Assuming reset clears reg_out when reset=0
• Ignoring clock edge sensitivity
• Confusing blocking and non-blocking assignments

4.

Identify the error in this Verilog register code snippet:

always @(posedge clk) begin
  if (reset == 1)
    reg_data = 8'b0;
  else
    reg_data <= input_data;
end

medium

A. Incorrect bit width for reg_data

B. Missing sensitivity to reset signal

C. Using blocking assignment (=) for reset instead of non-blocking (<=)

D. Using '==' instead of '=' in if condition

Solution

1. Step 1: Review assignment types in sequential blocks

   Inside always @(posedge clk), non-blocking assignments (<=) should be used for registers to avoid race conditions.

2. Step 2: Identify the error in reset assignment

   The reset assignment uses blocking '=' which is incorrect; it should be '<=' to match the else branch.

3. Final Answer:

   Using blocking assignment (=) for reset instead of non-blocking (<=) -> Option C

4. Quick Check:

   Use <= for all register assignments in clocked always blocks [OK]

Hint: Use <= for all assignments inside clocked always blocks [OK]

Common Mistakes:

• Mixing blocking and non-blocking assignments
• Not including reset in sensitivity list (not error here but common)
• Using '==' in if condition is correct syntax

5.

You want to create a parameterized multi-bit register module with asynchronous reset that can hold WIDTH bits. Which of the following code snippets correctly implements this?

module param_reg #(parameter WIDTH = 8) (
  input clk,
  input reset,
  input [WIDTH-1:0] data_in,
  output reg [WIDTH-1:0] data_out
);
  always @(posedge clk or posedge reset) begin
    if (reset)
      data_out <= {WIDTH{1'b0}};
    else
      data_out <= data_in;
  end
endmodule

hard

A. Incorrect: data_out declared as wire instead of reg

B. Incorrect: missing parameter declaration

C. Incorrect: synchronous reset used instead of asynchronous

D. Correct parameterized register with asynchronous reset

Solution

1. Step 1: Check parameter usage

   The module declares parameter WIDTH and uses it to size inputs and outputs correctly.

2. Step 2: Verify asynchronous reset and assignments

   The always block triggers on posedge clk or reset, and reset asynchronously clears data_out using replication operator.

3. Step 3: Confirm data_out declared as reg

   data_out is declared as reg, which is required for assignment inside always block.

4. Final Answer:

   Correct parameterized register with asynchronous reset -> Option D

5. Quick Check:

   Parameter + async reset + reg output = correct [OK]

Hint: Use parameter and replication operator for flexible reset [OK]

Common Mistakes:

• Forgetting parameter declaration
• Using synchronous reset when async needed
• Declaring output as wire instead of reg