Register (multi-bit flip-flop) in Verilog - Step-by-Step Execution

Concept Flow - Register (multi-bit flip-flop)

Start

↓

Wait for clock edge

↓

On rising edge?

No→Wait

Yes↓

Load input data into register

↓

Hold data stable

↓

Output register value

↓

Repeat on next clock edge

This flow shows how a multi-bit register waits for a clock signal, then loads and holds data on each rising clock edge.

Execution Sample

Verilog

module register(clk, reset, d, q);
  input clk, reset;
  input [3:0] d;
  output reg [3:0] q;

  always @(posedge clk or posedge reset) begin
    if (reset) q <= 4'b0000;
    else q <= d;
  end
endmodule

This Verilog code defines a 4-bit register that loads input d into q on the rising clock edge or resets q to zero.

Execution Table

Step	clk	reset	d	Condition	Action	q (register output)
1	0	1	4'b1010	reset=1?	Yes, q <= 0000	0000
2	1 (rising edge)	0	4'b1010	reset=0?	Load d into q	1010
3	0	0	4'b1100	No clock edge	Hold q	1010
4	1 (rising edge)	0	4'b1100	reset=0?	Load d into q	1100
5	0	0	4'b1111	No clock edge	Hold q	1100
6	1 (rising edge)	0	4'b1111	reset=0?	Load d into q	1111
7	1 (rising edge)	1	4'b0001	reset=1?	Reset q to 0000	0000

💡 Simulation ends after reset is asserted again, register output reset to zero.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7
clk	0	0	1	0	1	0	1	1
reset	0	1	0	0	0	0	0	1
d	0000	1010	1010	1100	1100	1111	1111	0001
q	0000	0000	1010	1010	1100	1100	1111	0000

Key Moments - 3 Insights

Why does the register output q change only on the rising edge of clk?

Because the always block triggers only on posedge clk or posedge reset, so q updates only when clk rises or reset is active, as shown in steps 2, 4, 6, and 7.

What happens to q when reset is high, even if clk is not rising?

When reset is high, q is immediately set to zero regardless of clk, as seen in step 1 and step 7 in the execution_table.

Why does q hold its value when clk is low or no rising edge occurs?

Because the always block does not trigger without a rising edge on clk or reset, so q keeps its previous value, shown in steps 3 and 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of q after step 4?

A 1100

B 1010

C 0000

D 1111

💡 Hint

Check the 'q' column in row for step 4 in execution_table.

At which step does the reset signal cause q to become 0000?

A Step 4

B Step 1

C Step 2

D Step 6

💡 Hint

Look for steps where reset=1 and q is set to 0000 in execution_table.

If the reset signal stayed low, what would q be after step 7?

A 0000

B 1010

C 1111

D 1100

💡 Hint

Refer to variable_tracker for q values and consider reset effect at step 7.

Concept Snapshot

Register (multi-bit flip-flop) in Verilog:
- Use always @(posedge clk or posedge reset) block
- On reset=1, set q to zero
- On rising clk, load input d into q
- q holds value between clock edges
- Useful for storing multi-bit data synchronously

Full Transcript

This visual execution trace shows a 4-bit register in Verilog. The register waits for a rising clock edge or a reset signal. When reset is high, the register output q is set to zero immediately. On each rising clock edge, if reset is low, the input data d is loaded into q. Between clock edges, q holds its value stable. The execution table traces each step with clk, reset, d, and q values. The variable tracker shows how signals change over time. Key moments clarify why q updates only on clock edges or reset, and why it holds value otherwise. The quiz questions test understanding of q's value changes and reset behavior. This helps beginners see how a multi-bit flip-flop register works step-by-step.