Register (multi-bit flip-flop) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named 'reg_out'.

Verilog

reg [1] reg_out;

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Awire

Binput

Coutput

D[3:0]

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'wire' instead of 'reg' for a register.

Not specifying the bit width with brackets.

The declaration reg [3:0] reg_out; creates a 4-bit register named reg_out.

2fill in blank

medium

Complete the always block sensitivity list to trigger on the positive edge of clock 'clk'.

Verilog

always @([1] clk) begin
  // register logic
end

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Anegedge

Blevel

Cposedge

Dedge

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge' instead of 'posedge' when positive edge is required.

Omitting 'posedge' or 'negedge' keyword.

The sensitivity list posedge clk triggers the always block on the rising edge of the clock signal.

3fill in blank

hard

Fix the error in the register assignment inside the always block.

Verilog

always @(posedge clk) begin
  reg_out [1] data_in;
end

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A!=

B<=

C==

D=

Attempts:

3 left

💡 Hint

Common Mistakes

Using blocking assignment '=' inside clocked always blocks.

Using comparison operators '==' or '!=' instead of assignment.

Non-blocking assignment <= is used inside clocked always blocks to model flip-flops correctly.

4fill in blank

hard

Fill both blanks to complete the reset logic for the register (active high synchronous reset).

Verilog

always @(posedge clk) begin
  if ([1]) begin
    reg_out [2] 4'b0000;
  end else begin
    reg_out <= data_in;
  end
end

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Areset

Bclk

C<=

D=

Attempts:

3 left

💡 Hint

Common Mistakes

Using blocking assignment '=' inside the always block for registers.

Checking the wrong signal in the if condition.

The reset signal is checked in the if condition, and the register is assigned zero using non-blocking assignment '<=' inside the always block.

5fill in blank

hard

Fill all three blanks to complete a parameterized register module with width 'WIDTH'.

Verilog

module register #(parameter WIDTH = [1]) (
  input wire clk,
  input wire reset,
  input wire [WIDTH-1:0] data_in,
  output reg [WIDTH-1:0] reg_out
);

always @(posedge clk) begin
  if (reset) begin
    reg_out [2] [3]'b0;
  end else begin
    reg_out <= data_in;
  end
end

endmodule

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A8

B<=

CWIDTH

D=

Attempts:

3 left

💡 Hint

Common Mistakes

Using blocking assignment '=' inside the always block.

Not using the parameter WIDTH for the reset value width.

The parameter WIDTH is set to 8 by default. The register uses non-blocking assignment '<=' to assign zero of WIDTH bits on reset.