Register (multi-bit flip-flop) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit register with synchronous reset

What is the output q of this 4-bit register after the rising edge of the clock if reset is high?

Assume initial q = 4'b1010 and d = 4'b1100.

Verilog

module reg4bit(input clk, input reset, input [3:0] d, output reg [3:0] q);
  always @(posedge clk) begin
    if (reset)
      q <= 4'b0000;
    else
      q <= d;
  end
endmodule

A q = 4'b0000

B q = 4'b1010

C q = 4'b1100

D q = 4'b1111

💡 Hint

Remember that synchronous reset sets the output to zero on clock edge when reset is high.

When reset is high at the clock's rising edge, the register output q is set to zero regardless of d.

❓ Predict Output

intermediate

Value of a 3-bit register after multiple clock cycles

Given this 3-bit register with asynchronous reset, what is the value of q after the second rising edge of clk?

Initial q = 3'b011, d = 3'b101, and reset is low during both clock edges.

Verilog

module reg3bit(input clk, input reset, input [2:0] d, output reg [2:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 3'b000;
    else
      q <= d;
  end
endmodule

A q = 3'b111

B q = 3'b011

C q = 3'b000

D q = 3'b101

💡 Hint

Asynchronous reset is not active, so register loads d on clock edges.

Since reset is low, on each rising clock edge, q updates to d. After the second clock edge, q remains 3'b101.

🔧 Debug

advanced

Identify the error in this 8-bit register code

This 8-bit register code is intended to load data d on the rising edge of clk. What error will occur when compiling or simulating this code?

Verilog

module reg8bit(input clk, input [7:0] d, output reg [7:0] q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A No error; code works as intended

B Synthesis warning: use non-blocking assignment '<=' inside always block for registers

C Syntax error: missing semicolon after 'q = d'

D Runtime error: q never updates

💡 Hint

Consider the difference between blocking '=' and non-blocking '<=' assignments in sequential logic.

In sequential always blocks triggered by clock edges, non-blocking assignments '<=' should be used to avoid simulation mismatches and synthesis warnings.

📝 Syntax

advanced

Syntax error in multi-bit register declaration

Which option contains the correct syntax to declare a 16-bit register named reg_data?

A reg [0:15] reg_data;

B reg [15:0] reg_data;

C reg reg_data : 16;

D reg reg_data[15:0];

💡 Hint

In Verilog, the bit range is declared inside square brackets before the variable name.

Option B uses the correct syntax: 'reg [15:0] reg_data;' declares a 16-bit register from bit 15 down to 0.

🚀 Application

expert

Number of bits flipped in a 5-bit register after input change

A 5-bit register q initially holds 5'b10101. On the next clock edge, it loads d = 5'b11011. How many bits in q will flip (change value) after the clock edge?

A 4

B 2

C 3

D 1

💡 Hint

Compare each bit of the initial and new values to count differences.

Comparing bits: 1->1 (no change), 0->1 (flip), 1->0 (flip), 0->1 (flip), 1->1 (no change). Total flips = 3.

Practice

1.

What is the main purpose of a multi-bit register in Verilog?

easy

A. To store multiple bits of data and update them on clock edges

B. To perform arithmetic operations on data

C. To generate clock signals

D. To convert analog signals to digital

Solution

1. Step 1: Understand the function of a register

   A register is used to hold data bits temporarily in digital circuits.

2. Step 2: Recognize clock edge behavior

   Registers update their stored data only on clock edges, making them synchronous storage elements.

3. Final Answer:

   To store multiple bits of data and update them on clock edges -> Option A

4. Quick Check:

   Register = multi-bit storage updated on clock edges [OK]

Hint: Registers store bits and update only on clock edges [OK]

Common Mistakes:

• Confusing registers with combinational logic
• Thinking registers generate clocks
• Assuming registers perform arithmetic

2.

Which of the following is the correct way to declare an 8-bit register in Verilog?

?

easy

A. reg [7:0] my_reg;

B. reg my_reg[7:0];

C. register [8] my_reg;

D. reg my_reg : 8;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with 'reg' keyword followed by bit range in square brackets before the name.

2. Step 2: Check each option

   reg [7:0] my_reg; uses correct syntax: 'reg [7:0] my_reg;'. Others have syntax errors or wrong keywords.

3. Final Answer:

   reg [7:0] my_reg; -> Option A

4. Quick Check:

   Correct reg declaration = reg [7:0] name; [OK]

Hint: Use reg [MSB:LSB] name; to declare multi-bit registers [OK]

Common Mistakes:

• Placing bit range after variable name
• Using 'register' keyword instead of 'reg'
• Using colon instead of square brackets

3.

Given the following Verilog code, what will be the value of reg_out after the positive edge of clk if reset is 0 and data_in is 8'b10101010?

module reg_example(input clk, input reset, input [7:0] data_in, output reg [7:0] reg_out);
  always @(posedge clk or posedge reset) begin
    if (reset)
      reg_out <= 8'b00000000;
    else
      reg_out <= data_in;
  end
endmodule

medium

A. 8'b00000000

B. 8'b10101010

C. 8'b11111111

D. No change in reg_out

Solution

1. Step 1: Analyze the always block sensitivity

   The block triggers on positive edge of clk or reset. If reset is high, reg_out resets to zero.

2. Step 2: Check conditions given

   Reset is 0, so reg_out will be assigned data_in value on clk rising edge, which is 8'b10101010.

3. Final Answer:

   8'b10101010 -> Option B

4. Quick Check:

   Reset=0, reg_out = data_in = 10101010 [OK]

Hint: If reset=0, reg_out updates to data_in on clk edge [OK]

Common Mistakes:

• Assuming reset clears reg_out when reset=0
• Ignoring clock edge sensitivity
• Confusing blocking and non-blocking assignments

4.

Identify the error in this Verilog register code snippet:

always @(posedge clk) begin
  if (reset == 1)
    reg_data = 8'b0;
  else
    reg_data <= input_data;
end

medium

A. Incorrect bit width for reg_data

B. Missing sensitivity to reset signal

C. Using blocking assignment (=) for reset instead of non-blocking (<=)

D. Using '==' instead of '=' in if condition

Solution

1. Step 1: Review assignment types in sequential blocks

   Inside always @(posedge clk), non-blocking assignments (<=) should be used for registers to avoid race conditions.

2. Step 2: Identify the error in reset assignment

   The reset assignment uses blocking '=' which is incorrect; it should be '<=' to match the else branch.

3. Final Answer:

   Using blocking assignment (=) for reset instead of non-blocking (<=) -> Option C

4. Quick Check:

   Use <= for all register assignments in clocked always blocks [OK]

Hint: Use <= for all assignments inside clocked always blocks [OK]

Common Mistakes:

• Mixing blocking and non-blocking assignments
• Not including reset in sensitivity list (not error here but common)
• Using '==' in if condition is correct syntax

5.

You want to create a parameterized multi-bit register module with asynchronous reset that can hold WIDTH bits. Which of the following code snippets correctly implements this?

module param_reg #(parameter WIDTH = 8) (
  input clk,
  input reset,
  input [WIDTH-1:0] data_in,
  output reg [WIDTH-1:0] data_out
);
  always @(posedge clk or posedge reset) begin
    if (reset)
      data_out <= {WIDTH{1'b0}};
    else
      data_out <= data_in;
  end
endmodule

hard

A. Incorrect: data_out declared as wire instead of reg

B. Incorrect: missing parameter declaration

C. Incorrect: synchronous reset used instead of asynchronous

D. Correct parameterized register with asynchronous reset

Solution

1. Step 1: Check parameter usage

   The module declares parameter WIDTH and uses it to size inputs and outputs correctly.

2. Step 2: Verify asynchronous reset and assignments

   The always block triggers on posedge clk or reset, and reset asynchronously clears data_out using replication operator.

3. Step 3: Confirm data_out declared as reg

   data_out is declared as reg, which is required for assignment inside always block.

4. Final Answer:

   Correct parameterized register with asynchronous reset -> Option D

5. Quick Check:

   Parameter + async reset + reg output = correct [OK]

Hint: Use parameter and replication operator for flexible reset [OK]

Common Mistakes:

• Forgetting parameter declaration
• Using synchronous reset when async needed
• Declaring output as wire instead of reg