Register (multi-bit flip-flop) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit register with synchronous reset

What is the output q of this 4-bit register after the rising edge of the clock if reset is high?

Assume initial q = 4'b1010 and d = 4'b1100.

Verilog

module reg4bit(input clk, input reset, input [3:0] d, output reg [3:0] q);
  always @(posedge clk) begin
    if (reset)
      q <= 4'b0000;
    else
      q <= d;
  end
endmodule

A q = 4'b0000

B q = 4'b1010

C q = 4'b1100

D q = 4'b1111

💡 Hint

Remember that synchronous reset sets the output to zero on clock edge when reset is high.

When reset is high at the clock's rising edge, the register output q is set to zero regardless of d.

❓ Predict Output

intermediate

Value of a 3-bit register after multiple clock cycles

Given this 3-bit register with asynchronous reset, what is the value of q after the second rising edge of clk?

Initial q = 3'b011, d = 3'b101, and reset is low during both clock edges.

Verilog

module reg3bit(input clk, input reset, input [2:0] d, output reg [2:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 3'b000;
    else
      q <= d;
  end
endmodule

A q = 3'b111

B q = 3'b011

C q = 3'b000

D q = 3'b101

💡 Hint

Asynchronous reset is not active, so register loads d on clock edges.

Since reset is low, on each rising clock edge, q updates to d. After the second clock edge, q remains 3'b101.

🔧 Debug

advanced

Identify the error in this 8-bit register code

This 8-bit register code is intended to load data d on the rising edge of clk. What error will occur when compiling or simulating this code?

Verilog

module reg8bit(input clk, input [7:0] d, output reg [7:0] q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A No error; code works as intended

B Synthesis warning: use non-blocking assignment '<=' inside always block for registers

C Syntax error: missing semicolon after 'q = d'

D Runtime error: q never updates

💡 Hint

Consider the difference between blocking '=' and non-blocking '<=' assignments in sequential logic.

In sequential always blocks triggered by clock edges, non-blocking assignments '<=' should be used to avoid simulation mismatches and synthesis warnings.

📝 Syntax

advanced

Syntax error in multi-bit register declaration

Which option contains the correct syntax to declare a 16-bit register named reg_data?

A reg [0:15] reg_data;

B reg [15:0] reg_data;

C reg reg_data : 16;

D reg reg_data[15:0];

💡 Hint

In Verilog, the bit range is declared inside square brackets before the variable name.

Option B uses the correct syntax: 'reg [15:0] reg_data;' declares a 16-bit register from bit 15 down to 0.

🚀 Application

expert

Number of bits flipped in a 5-bit register after input change

A 5-bit register q initially holds 5'b10101. On the next clock edge, it loads d = 5'b11011. How many bits in q will flip (change value) after the clock edge?

A 4

B 2

C 3

D 1

💡 Hint

Compare each bit of the initial and new values to count differences.

Comparing bits: 1->1 (no change), 0->1 (flip), 1->0 (flip), 0->1 (flip), 1->1 (no change). Total flips = 3.