Register (multi-bit flip-flop) in Verilog - Mini Project: Build & Apply

Register (multi-bit flip-flop) in Verilog

📖 Scenario: You are designing a simple digital circuit that stores a 4-bit value. This is like a small memory box that remembers the bits when a clock signal ticks.

🎯 Goal: Build a 4-bit register using flip-flops in Verilog. The register should store the input value on the rising edge of the clock when the enable signal is high.

📋 What You'll Learn

Create a 4-bit input called data_in

Create a 4-bit output called data_out

Create an input clock signal called clk

Create an input enable signal called en

On the rising edge of clk, if en is high, store data_in into the register

Otherwise, keep the previous value

💡 Why This Matters

🌍 Real World

Registers like this are used in CPUs and digital devices to hold temporary data during processing.

💼 Career

Understanding registers is essential for hardware design engineers and anyone working with digital circuits or FPGA programming.

1

Create module and inputs/outputs

Write a Verilog module named Register4bit with inputs clk, en, and 4-bit input data_in. Also create a 4-bit output data_out.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

// Your code here

endmodule

Need a hint?

Define the module and declare inputs and outputs exactly as named.

2

Add register storage variable

Inside the Register4bit module, declare a 4-bit register variable named reg_data to hold the stored value.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;
// Your code here

endmodule

Need a hint?

Use reg [3:0] reg_data; to declare the storage register.

3

Add always block for storing data

Add an always @(posedge clk) block inside Register4bit. Inside it, write an if statement that checks if en is high. If yes, assign data_in to reg_data. Otherwise, keep reg_data unchanged.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;

always @(posedge clk) begin
    // Your code here
end

endmodule

Need a hint?

Use non-blocking assignment <= inside the always block for registers.

4

Assign output from register and test

Assign data_out to the value of reg_data continuously. Then write a testbench code snippet that creates a Register4bit instance, applies clock and enable signals, and prints data_out after storing 4'b1010. Use $display to print the output.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;

always @(posedge clk) begin
    if (en) begin
        reg_data <= data_in;
    end
end

assign data_out = reg_data;

endmodule

// Your testbench code here

Need a hint?

Use assign or an always @(*) block to connect data_out to reg_data. In the testbench, toggle clk and use $display to print data_out.