Register (multi-bit flip-flop) in Verilog - Mini Project: Build & Apply

Register (multi-bit flip-flop) in Verilog

📖 Scenario: You are designing a simple digital circuit that stores a 4-bit value. This is like a small memory box that remembers the bits when a clock signal ticks.

🎯 Goal: Build a 4-bit register using flip-flops in Verilog. The register should store the input value on the rising edge of the clock when the enable signal is high.

📋 What You'll Learn

Create a 4-bit input called data_in

Create a 4-bit output called data_out

Create an input clock signal called clk

Create an input enable signal called en

On the rising edge of clk, if en is high, store data_in into the register

Otherwise, keep the previous value

💡 Why This Matters

🌍 Real World

Registers like this are used in CPUs and digital devices to hold temporary data during processing.

💼 Career

Understanding registers is essential for hardware design engineers and anyone working with digital circuits or FPGA programming.

1

Create module and inputs/outputs

Write a Verilog module named Register4bit with inputs clk, en, and 4-bit input data_in. Also create a 4-bit output data_out.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

// Your code here

endmodule

Hint

Define the module and declare inputs and outputs exactly as named.

2

Add register storage variable

Inside the Register4bit module, declare a 4-bit register variable named reg_data to hold the stored value.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;
// Your code here

endmodule

Hint

Use reg [3:0] reg_data; to declare the storage register.

3

Add always block for storing data

Add an always @(posedge clk) block inside Register4bit. Inside it, write an if statement that checks if en is high. If yes, assign data_in to reg_data. Otherwise, keep reg_data unchanged.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;

always @(posedge clk) begin
    // Your code here
end

endmodule

Hint

Use non-blocking assignment <= inside the always block for registers.

4

Assign output from register and test

Assign data_out to the value of reg_data continuously. Then write a testbench code snippet that creates a Register4bit instance, applies clock and enable signals, and prints data_out after storing 4'b1010. Use $display to print the output.

Verilog

module Register4bit(
    input clk,
    input en,
    input [3:0] data_in,
    output reg [3:0] data_out
);

reg [3:0] reg_data;

always @(posedge clk) begin
    if (en) begin
        reg_data <= data_in;
    end
end

assign data_out = reg_data;

endmodule

// Your testbench code here

Hint

Use assign or an always @(*) block to connect data_out to reg_data. In the testbench, toggle clk and use $display to print data_out.

Practice

1.

What is the main purpose of a multi-bit register in Verilog?

easy

A. To store multiple bits of data and update them on clock edges

B. To perform arithmetic operations on data

C. To generate clock signals

D. To convert analog signals to digital

Solution

1. Step 1: Understand the function of a register

   A register is used to hold data bits temporarily in digital circuits.

2. Step 2: Recognize clock edge behavior

   Registers update their stored data only on clock edges, making them synchronous storage elements.

3. Final Answer:

   To store multiple bits of data and update them on clock edges -> Option A

4. Quick Check:

   Register = multi-bit storage updated on clock edges [OK]

Hint: Registers store bits and update only on clock edges [OK]

Common Mistakes:

• Confusing registers with combinational logic
• Thinking registers generate clocks
• Assuming registers perform arithmetic

2.

Which of the following is the correct way to declare an 8-bit register in Verilog?

?

easy

A. reg [7:0] my_reg;

B. reg my_reg[7:0];

C. register [8] my_reg;

D. reg my_reg : 8;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with 'reg' keyword followed by bit range in square brackets before the name.

2. Step 2: Check each option

   reg [7:0] my_reg; uses correct syntax: 'reg [7:0] my_reg;'. Others have syntax errors or wrong keywords.

3. Final Answer:

   reg [7:0] my_reg; -> Option A

4. Quick Check:

   Correct reg declaration = reg [7:0] name; [OK]

Hint: Use reg [MSB:LSB] name; to declare multi-bit registers [OK]

Common Mistakes:

• Placing bit range after variable name
• Using 'register' keyword instead of 'reg'
• Using colon instead of square brackets

3.

Given the following Verilog code, what will be the value of reg_out after the positive edge of clk if reset is 0 and data_in is 8'b10101010?

module reg_example(input clk, input reset, input [7:0] data_in, output reg [7:0] reg_out);
  always @(posedge clk or posedge reset) begin
    if (reset)
      reg_out <= 8'b00000000;
    else
      reg_out <= data_in;
  end
endmodule

medium

A. 8'b00000000

B. 8'b10101010

C. 8'b11111111

D. No change in reg_out

Solution

1. Step 1: Analyze the always block sensitivity

   The block triggers on positive edge of clk or reset. If reset is high, reg_out resets to zero.

2. Step 2: Check conditions given

   Reset is 0, so reg_out will be assigned data_in value on clk rising edge, which is 8'b10101010.

3. Final Answer:

   8'b10101010 -> Option B

4. Quick Check:

   Reset=0, reg_out = data_in = 10101010 [OK]

Hint: If reset=0, reg_out updates to data_in on clk edge [OK]

Common Mistakes:

• Assuming reset clears reg_out when reset=0
• Ignoring clock edge sensitivity
• Confusing blocking and non-blocking assignments

4.

Identify the error in this Verilog register code snippet:

always @(posedge clk) begin
  if (reset == 1)
    reg_data = 8'b0;
  else
    reg_data <= input_data;
end

medium

A. Incorrect bit width for reg_data

B. Missing sensitivity to reset signal

C. Using blocking assignment (=) for reset instead of non-blocking (<=)

D. Using '==' instead of '=' in if condition

Solution

1. Step 1: Review assignment types in sequential blocks

   Inside always @(posedge clk), non-blocking assignments (<=) should be used for registers to avoid race conditions.

2. Step 2: Identify the error in reset assignment

   The reset assignment uses blocking '=' which is incorrect; it should be '<=' to match the else branch.

3. Final Answer:

   Using blocking assignment (=) for reset instead of non-blocking (<=) -> Option C

4. Quick Check:

   Use <= for all register assignments in clocked always blocks [OK]

Hint: Use <= for all assignments inside clocked always blocks [OK]

Common Mistakes:

• Mixing blocking and non-blocking assignments
• Not including reset in sensitivity list (not error here but common)
• Using '==' in if condition is correct syntax

5.

You want to create a parameterized multi-bit register module with asynchronous reset that can hold WIDTH bits. Which of the following code snippets correctly implements this?

module param_reg #(parameter WIDTH = 8) (
  input clk,
  input reset,
  input [WIDTH-1:0] data_in,
  output reg [WIDTH-1:0] data_out
);
  always @(posedge clk or posedge reset) begin
    if (reset)
      data_out <= {WIDTH{1'b0}};
    else
      data_out <= data_in;
  end
endmodule

hard

A. Incorrect: data_out declared as wire instead of reg

B. Incorrect: missing parameter declaration

C. Incorrect: synchronous reset used instead of asynchronous

D. Correct parameterized register with asynchronous reset

Solution

1. Step 1: Check parameter usage

   The module declares parameter WIDTH and uses it to size inputs and outputs correctly.

2. Step 2: Verify asynchronous reset and assignments

   The always block triggers on posedge clk or reset, and reset asynchronously clears data_out using replication operator.

3. Step 3: Confirm data_out declared as reg

   data_out is declared as reg, which is required for assignment inside always block.

4. Final Answer:

   Correct parameterized register with asynchronous reset -> Option D

5. Quick Check:

   Parameter + async reset + reg output = correct [OK]

Hint: Use parameter and replication operator for flexible reset [OK]

Common Mistakes:

• Forgetting parameter declaration
• Using synchronous reset when async needed
• Declaring output as wire instead of reg