Modulo-N counter in Verilog - Step-by-Step Execution

Concept Flow - Modulo-N counter

Start: count = 0

↓

Check: count < N-1?

No→Reset count to 0

Yes↓

Increment count by 1

↓

Output count

↩Back to Check

The counter starts at 0, increments by 1 each clock cycle until it reaches N-1, then resets to 0 and repeats.

Execution Sample

Verilog

always @(posedge clk) begin
  if (count == N-1)
    count <= 0;
  else
    count <= count + 1;
end

This code increments the count on each clock pulse and resets it to zero when it reaches N-1.

Execution Table

Clock Cycle	count Before	Condition (count == N-1)	Action	count After	Output
1	0	False	Increment count	1	1
2	1	False	Increment count	2	2
3	2	False	Increment count	3	3
4	3	False	Increment count	4	4
5	4	True	Reset count to 0	0	0
6	0	False	Increment count	1	1

💡 The counter resets to 0 after reaching N-1 (4 in this example), then continues counting.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
count	0	1	2	3	4	0	1

Key Moments - 2 Insights

Why does the count reset to 0 after reaching N-1?

Because the condition 'count == N-1' becomes true (see execution_table row 5), triggering the reset action to keep the count within 0 to N-1.

What happens if the condition is false?

The count increments by 1 (see execution_table rows 1-4 and 6), moving the counter forward.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after clock cycle 3?

A 3

B 2

C 4

D 0

💡 Hint

Check the 'count After' column for clock cycle 3 in the execution_table.

At which clock cycle does the count reset to 0?

A 4

B 5

C 6

D 3

💡 Hint

Look for the row where the condition 'count == N-1' is true and action is 'Reset count to 0' in the execution_table.

If N was 3 instead of 5, what would happen at clock cycle 3?

A count stays at 3

B count increments to 4

C count resets to 0

D count increments to 3

💡 Hint

Since N-1 would be 2, count resets to 0 when it reaches 2, so at cycle 3 it resets.

Concept Snapshot

Modulo-N counter in Verilog:
- Counts from 0 up to N-1
- On each clock pulse, increments count
- Resets to 0 when count == N-1
- Keeps count within 0 to N-1 range
- Useful for cyclic counting tasks

Full Transcript

This visual execution trace shows a modulo-N counter in Verilog. The counter starts at zero and increments by one on each clock cycle. When the count reaches N-1, it resets back to zero. The execution table tracks the count value before and after each clock cycle, the condition check, and the action taken. The variable tracker shows how the count changes over time. Key moments clarify why the counter resets and what happens when the condition is false. The quiz tests understanding of count values at specific cycles and behavior changes if N changes.

Practice

1.

What does a modulo-N counter do in Verilog?

easy

A. Counts from 0 up to N-1 and then restarts at 0

B. Counts only once and stops

C. Counts from N down to 0 and stops

D. Counts randomly between 0 and N

Solution

1. Step 1: Understand the counting range

   A modulo-N counter counts numbers starting from 0 up to N-1.

2. Step 2: Recognize the reset behavior

   After reaching N-1, it restarts counting from 0 again, repeating the cycle.

3. Final Answer:

   Counts from 0 up to N-1 and then restarts at 0 -> Option A

4. Quick Check:

   Modulo-N counter = counts 0 to N-1 then resets [OK]

Hint: Modulo-N means count up to N-1 then restart at zero [OK]

Common Mistakes:

• Thinking it counts down instead of up
• Assuming it stops after one cycle
• Confusing modulo-N with random counting

2.

Which of the following is the correct Verilog syntax to declare a 4-bit register count for a modulo-16 counter?

easy

A. wire [3:0] count;

B. reg [4:0] count;

C. reg [3:0] count;

D. integer count;

Solution

1. Step 1: Determine bit width for modulo-16

   Modulo-16 means counting 0 to 15, which fits in 4 bits (2^4=16).

2. Step 2: Choose correct register declaration

   Use reg [3:0] count; to declare a 4-bit register named count.

3. Final Answer:

   reg [3:0] count; -> Option C

4. Quick Check:

   4 bits needed for 16 states [OK]

Hint: 4 bits hold 0 to 15, so use reg [3:0] [OK]

Common Mistakes:

• Using wire instead of reg for a counter
• Using 5 bits instead of 4 bits
• Using integer which is not fixed bit width

3.

What is the output sequence of count in this Verilog code snippet for a modulo-4 counter after 6 clock cycles (assuming reset is low)?

reg [1:0] count = 0;
always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else if (count == 3)
    count <= 0;
  else
    count <= count + 1;
end

medium

A. [0, 1, 2, 0, 1, 2]

B. [1, 2, 3, 0, 1, 2]

C. [0, 1, 2, 3, 4, 5]

D. [0, 1, 2, 3, 0, 1]

Solution

1. Step 1: Trace count values per clock

   Starting at 0, count increments each clock until 3, then resets to 0:
   Cycle 1: 0
   Cycle 2: 1
   Cycle 3: 2
   Cycle 4: 3
   Cycle 5: 0 (reset)
   Cycle 6: 1

2. Step 2: Confirm sequence length and values

   Sequence after 6 cycles is [0, 1, 2, 3, 0, 1].

3. Final Answer:

   [0, 1, 2, 3, 0, 1] -> Option D

4. Quick Check:

   Modulo-4 cycles 0 to 3 then repeats [OK]

Hint: Count resets after reaching N-1, so watch the reset step [OK]

Common Mistakes:

• Counting beyond 3 (like 4 or 5)
• Starting count at 1 instead of 0
• Forgetting reset condition when count == 3

4.

Identify the error in this Verilog code for a modulo-8 counter:

reg [2:0] count;
always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else if (count == 8)
    count <= 0;
  else
    count <= count + 1;
end

medium

A. The register width is too large for modulo-8

B. The condition should be 'count == 7' instead of 'count == 8'

C. Reset should be in negedge, not posedge

D. The count variable should be declared as wire, not reg

Solution

1. Step 1: Check counting range for modulo-8

   Modulo-8 counts from 0 to 7, so max count is 7, not 8.

2. Step 2: Identify incorrect condition

   The code checks if count == 8, which is invalid since count cannot reach 8 with 3 bits.

3. Final Answer:

   The condition should be 'count == 7' instead of 'count == 8' -> Option B

4. Quick Check:

   Max count for 3 bits is 7, not 8 [OK]

Hint: Max count = 2^bits - 1, so check condition against 7 for 3 bits [OK]

Common Mistakes:

• Using count == 8 instead of count == 7
• Declaring count as wire instead of reg
• Misunderstanding reset edge sensitivity

5.

You want to design a modulo-10 counter in Verilog that counts from 0 to 9 and then resets to 0. Which code snippet correctly implements this behavior?

reg [3:0] count;
always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else if (count == 9)
    count <= 0;
  else
    count <= count + 1;
end

hard

A. This code is correct because 4 bits can represent 0 to 15, and count resets at 9.

B. This code is incorrect because 4 bits cannot represent 0 to 9.

C. This code is incorrect because count should reset at 10, not 9.

D. This code is incorrect because count should be declared as wire.

Solution

1. Step 1: Check bit width for modulo-10

   4 bits can represent values from 0 to 15, which covers 0 to 9 easily.

2. Step 2: Verify reset condition

   The code resets count to 0 when count reaches 9, correctly implementing modulo-10 behavior.

3. Final Answer:

   This code is correct because 4 bits can represent 0 to 15, and count resets at 9. -> Option A

4. Quick Check:

   4 bits cover 0-9; reset at 9 is correct [OK]

Hint: Use enough bits for max count; reset at N-1 for modulo-N [OK]

Common Mistakes:

• Thinking 4 bits can't hold 0 to 9
• Resetting count at 10 instead of 9
• Declaring count as wire instead of reg