Modulo-N counter in Verilog - Step-by-Step Execution

Concept Flow - Modulo-N counter

Start: count = 0

↓

Check: count < N-1?

No→Reset count to 0

Yes↓

Increment count by 1

↓

Output count

↩Back to Check

The counter starts at 0, increments by 1 each clock cycle until it reaches N-1, then resets to 0 and repeats.

Execution Sample

Verilog

always @(posedge clk) begin
  if (count == N-1)
    count <= 0;
  else
    count <= count + 1;
end

This code increments the count on each clock pulse and resets it to zero when it reaches N-1.

Execution Table

Clock Cycle	count Before	Condition (count == N-1)	Action	count After	Output
1	0	False	Increment count	1	1
2	1	False	Increment count	2	2
3	2	False	Increment count	3	3
4	3	False	Increment count	4	4
5	4	True	Reset count to 0	0	0
6	0	False	Increment count	1	1

💡 The counter resets to 0 after reaching N-1 (4 in this example), then continues counting.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
count	0	1	2	3	4	0	1

Key Moments - 2 Insights

Why does the count reset to 0 after reaching N-1?

Because the condition 'count == N-1' becomes true (see execution_table row 5), triggering the reset action to keep the count within 0 to N-1.

What happens if the condition is false?

The count increments by 1 (see execution_table rows 1-4 and 6), moving the counter forward.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after clock cycle 3?

A 3

B 2

C 4

D 0

💡 Hint

Check the 'count After' column for clock cycle 3 in the execution_table.

At which clock cycle does the count reset to 0?

A 4

B 5

C 6

D 3

💡 Hint

Look for the row where the condition 'count == N-1' is true and action is 'Reset count to 0' in the execution_table.

If N was 3 instead of 5, what would happen at clock cycle 3?

A count stays at 3

B count increments to 4

C count resets to 0

D count increments to 3

💡 Hint

Since N-1 would be 2, count resets to 0 when it reaches 2, so at cycle 3 it resets.

Concept Snapshot

Modulo-N counter in Verilog:
- Counts from 0 up to N-1
- On each clock pulse, increments count
- Resets to 0 when count == N-1
- Keeps count within 0 to N-1 range
- Useful for cyclic counting tasks

Full Transcript

This visual execution trace shows a modulo-N counter in Verilog. The counter starts at zero and increments by one on each clock cycle. When the count reaches N-1, it resets back to zero. The execution table tracks the count value before and after each clock cycle, the condition check, and the action taken. The variable tracker shows how the count changes over time. Key moments clarify why the counter resets and what happens when the condition is false. The quiz tests understanding of count values at specific cycles and behavior changes if N changes.