Modulo-N counter in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named 'count'.

Verilog

reg [3:0] [1] ;

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Acounter

Bcount

Cvalue

Dcnt

Attempts:

3 left

💡 Hint

Common Mistakes

Using a different register name like 'cnt' or 'counter'.

The register is named 'count' as required.

2fill in blank

medium

Complete the code to increment 'count' by 1 on each positive clock edge.

Verilog

always @(posedge clk) begin
  [1] <= count + 1;
end

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Acount

Bclk

Ccounter

Dvalue

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning to 'clk' or other unrelated signals.

'count' is the register being incremented.

3fill in blank

hard

Fix the error in the reset condition to set 'count' to zero when 'rst' is high.

Verilog

always @(posedge clk or posedge rst) begin
  if ([1]) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

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Arst

Bclk

Ccount

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Checking 'if (clk)' or 'if (enable)' instead of 'if (rst)'.

The reset signal is 'rst', so the condition should check 'if (rst)'.

4fill in blank

hard

Fill both blanks to complete the modulo-N counter that resets 'count' to zero when it reaches N-1.

Verilog

parameter N = 10;
always @(posedge clk or posedge rst) begin
  if (rst) begin
    count <= 0;
  end else if (count [1] N-1) begin
    count <= [2];
  end else begin
    count <= count + 1;
  end
end

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A==

B0

C>=

DN

Attempts:

3 left

💡 Hint

Common Mistakes

Using '>=' instead of '==' or resetting to N instead of 0.

The counter resets when count equals N-1, so use '==' and reset to 0.

5fill in blank

hard

Fill all three blanks to create a modulo-N counter with enable signal that increments only when enabled.

Verilog

parameter N = 8;
always @(posedge clk or posedge rst) begin
  if (rst) begin
    count <= 0;
  end else if ([1]) begin
    if (count [2] N-1) begin
      count <= [3];
    end else begin
      count <= count + 1;
    end
  end
end

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Aenable

B==

C0

D>=

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong condition for enable or comparison operators.

The counter increments only if 'enable' is true, resets to 0 when count equals N-1.