Modulo-N counter in Verilog - Mini Project: Build & Apply

Modulo-N Counter in Verilog

📖 Scenario: You are designing a simple digital counter that counts from 0 up to a number N-1 and then wraps back to 0. This is useful in many electronics projects like timers, clocks, or event counters.

🎯 Goal: Build a modulo_n_counter module in Verilog that counts from 0 to N-1 and then resets to 0 on the next clock cycle.

📋 What You'll Learn

Create a register to hold the current count.

Use a parameter N to set the modulo value.

Increment the counter on each positive clock edge.

Reset the counter to 0 when it reaches N-1.

Output the current count.

💡 Why This Matters

🌍 Real World

Modulo counters are used in digital clocks, timers, frequency dividers, and event counters in electronics.

💼 Career

Understanding counters is fundamental for hardware design engineers working with FPGAs, ASICs, and embedded systems.

1

Create the module and declare the counter register

Write a Verilog module named modulo_n_counter with inputs clk and rst, and an output count of 4 bits. Declare a 4-bit register called count_reg to hold the current count.

Verilog

module modulo_n_counter(input clk, input rst, output reg [3:0] count);
// Declare a 4-bit register called count_reg
// Your code here
endmodule

Need a hint?

Remember to declare count_reg as a 4-bit register inside the module.

2

Add parameter N for modulo value

Add a parameter N with value 10 to the modulo_n_counter module to set the modulo value.

Verilog

module modulo_n_counter(input clk, input rst, output reg [3:0] count);
    parameter N = 10;
    reg [3:0] count_reg;
// Your code here
endmodule

Need a hint?

Use the parameter keyword to define N inside the module.

3

Implement the counting logic with reset and modulo wrap

Inside an always @(posedge clk) block, write code that resets count_reg to 0 when rst is high. Otherwise, increment count_reg by 1. If count_reg reaches N-1, reset it to 0 on the next clock cycle.

Verilog

module modulo_n_counter(input clk, input rst, output reg [3:0] count);
    parameter N = 10;
    reg [3:0] count_reg;

    always @(posedge clk) begin
        // Reset count_reg to 0 if rst is high
        // Else increment count_reg
        // Wrap count_reg to 0 when it reaches N-1
        // Your code here
    end
endmodule

Need a hint?

Use non-blocking assignments <= inside the always block for registers.

4

Assign the output count from the register and display it

Assign the output count to the value of count_reg. Then write a testbench initial block that resets the counter, runs the clock for 15 cycles, and uses $display to print the count value on each cycle.

Verilog

module modulo_n_counter(input clk, input rst, output reg [3:0] count);
    parameter N = 10;
    reg [3:0] count_reg;

    always @(posedge clk) begin
        if (rst) begin
            count_reg <= 0;
        end else if (count_reg == N - 1) begin
            count_reg <= 0;
        end else begin
            count_reg <= count_reg + 1;
        end
    end

    // Assign count output
    // Your code here
endmodule

// Testbench module
module testbench();
    reg clk = 0;
    reg rst;
    wire [3:0] count;

    modulo_n_counter uut(.clk(clk), .rst(rst), .count(count));

    always #5 clk = ~clk; // Clock with period 10 units

    initial begin
        rst = 1;
        #10;
        rst = 0;
        // Run for 150 time units (15 clock cycles)
        repeat (15) begin
            @(posedge clk);
            $display("Count = %d", count);
        end
        $finish;
    end
endmodule

Need a hint?

Assign count to count_reg using a combinational block or continuous assignment. Use a testbench to simulate and print the count values.