Modulo-N counter in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple Modulo-4 counter

What is the output sequence of the 2-bit Modulo-4 counter after 5 clock cycles?

Consider the following Verilog code snippet:

Verilog

module mod4_counter(input clk, input reset, output reg [1:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 2'b00;
    else
      count <= (count == 2'b11) ? 2'b00 : count + 1;
  end
endmodule

A 0, 1, 2, 3, 4

B 1, 2, 3, 0, 1

C 0, 1, 2, 3, 0

D 0, 1, 2, 0, 1

💡 Hint

Remember the counter resets to 0 after reaching 3 (2'b11).

The counter counts from 0 to 3 (2'b00 to 2'b11) and then resets to 0. After 5 clock cycles starting from 0, the sequence is 0,1,2,3,0.

🧠 Conceptual

intermediate

Understanding Modulo-N counter reset behavior

In a Modulo-N counter implemented in Verilog, what is the purpose of the reset signal?

A To pause the counter temporarily

B To initialize the counter value to zero or a known state

C To increase the counting speed

D To change the counting direction

💡 Hint

Think about what happens when the system starts or needs to restart counting.

The reset signal sets the counter to a known starting value, usually zero, ensuring predictable behavior.

🔧 Debug

advanced

Identify the error in this Modulo-5 counter code

What error will occur when simulating this Modulo-5 counter Verilog code?

Verilog

module mod5_counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 3'b000;
    else if (count == 3'b101)
      count <= 3'b000;
    else
      count <= count + 1;
  end
endmodule

A The counter never resets because 3'b101 is 5 decimal, which is out of 3-bit range

B Runtime error because count is declared as 2 bits but assigned 3 bits

C Syntax error due to missing semicolon

D The counter resets correctly after counting to 5

💡 Hint

Check the binary value used for comparison and the bit width of count.

3'b101 is decimal 5, which is valid for 3 bits, but the counter counts from 0 to 4 for modulo 5. The condition should check for 3'b100 (decimal 4) to reset after 4, not 5.

📝 Syntax

advanced

Syntax error in Modulo-N counter code

Which option contains the correct syntax for a Modulo-3 counter in Verilog?

A always @(posedge clk or posedge reset) begin if(reset) count <= 2'b00; else if(count == 2'b10) count <= 2'b00; else count <= count + 1; end

B always @(posedge clk or posedge reset) begin if(reset) count = 2'b00; else if(count == 2'b11) count <= 2'b00; else count <= count + 1; end

C always @(posedge clk or posedge reset) begin if(reset) count <= 2'b00 else if(count == 2'b10) count <= 2'b00; else count <= count + 1; end

D always @(posedge clk or posedge reset) begin if(reset) count <= 2'b00; else if(count == 2'b10) count = 2'b00; else count <= count + 1; end

💡 Hint

Check for missing semicolons and correct use of non-blocking assignments.

Option A uses correct syntax with non-blocking assignments (<=) and proper semicolons. Option A uses blocking assignment (=) in a sequential block which is discouraged. Option A misses a semicolon after count <= 2'b00. Option A uses blocking assignment (=) in one place.

🚀 Application

expert

Design challenge: Modulo-6 counter output after 10 cycles

Given this Modulo-6 counter Verilog code, what is the value of 'count' after 10 positive clock edges starting from reset?

Code:
module mod6_counter(input clk, input reset, output reg [2:0] count);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 3'b000;
else if (count == 3'b101)
count <= 3'b000;
else
count <= count + 1;
end
endmodule

A 0 (3'b000)

B 3 (3'b011)

C 5 (3'b101)

D 4 (3'b100)

💡 Hint

Count the increments carefully and remember the counter resets after reaching 5.

The counter counts 0,1,2,3,4,5 then resets to 0. After 10 cycles starting at 0, the sequence is: 0,1,2,3,4,5,0,1,2,3, so the count after 10 cycles is 4.