FIFO buffer design concept in Verilog - Step-by-Step Execution

Concept Flow - FIFO buffer design concept

Start

↓

Write Data?

No→Wait

Yes↓

Check if Full?

Yes→Wait

No↓

Write Data to Buffer

↓

Update Write Pointer

↓

Read Data?

No→Wait

Yes↓

Check if Empty?

Yes→Wait

No↓

Read Data from Buffer

↓

Update Read Pointer

↓

Repeat

This flow shows how a FIFO buffer writes data when not full and reads data when not empty, updating pointers accordingly.

Execution Sample

Verilog

module fifo(
  input clk, reset,
  input wr_en, rd_en,
  input [3:0] data_in,
  output reg [3:0] data_out,
  output full, empty
);

This code snippet starts a FIFO module with clock, reset, write/read enables, data input/output, and status signals.

Execution Table

Step	Operation	Write Pointer (wr_ptr)	Read Pointer (rd_ptr)	Buffer Content	Full Flag	Empty Flag	Action
1	Reset	0	0	[_, _, _, _]	0	1	Initialize pointers and flags
2	Write Data=5, wr_en=1	0	0	[5, _, _, _]	0	0	Write 5 at position 0, wr_ptr=1
3	Write Data=9, wr_en=1	1	0	[5, 9, _, _]	0	0	Write 9 at position 1, wr_ptr=2
4	Read Data, rd_en=1	2	0	[5, 9, _, _]	0	0	Read 5 from position 0, rd_ptr=1
5	Write Data=3, wr_en=1	2	1	[5, 9, 3, _]	0	0	Write 3 at position 2, wr_ptr=3
6	Read Data, rd_en=1	3	1	[5, 9, 3, _]	0	0	Read 9 from position 1, rd_ptr=2
7	Write Data=7, wr_en=1	3	2	[5, 9, 3, 7]	1	0	Write 7 at position 3, wr_ptr=0 (wrap), buffer full
8	Read Data, rd_en=1	0	2	[5, 9, 3, 7]	0	0	Read 3 from position 2, rd_ptr=3, buffer not full
9	Read Data, rd_en=1	0	3	[5, 9, 3, 7]	0	0	Read 7 from position 3, rd_ptr=0 (wrap)
10	Read Data, rd_en=1	0	0	[5, 9, 3, 7]	0	1	Buffer empty after reading all data
11	Write Data=2, wr_en=1	0	0	[2, 9, 3, 7]	0	0	Write 2 at position 0, wr_ptr=1
12	Stop	-	-	-	-	-	End of trace

💡 Execution stops after demonstrating full and empty conditions with pointer wrap-around.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
wr_ptr	0	1	2	2	3	3	0	0	0	0	0	1	1
rd_ptr	0	0	0	1	1	2	2	3	3	0	0	0	0
full	0	0	0	0	0	0	1	0	0	0	0	0	0
empty	1	0	0	0	0	0	0	0	0	1	0	0	0
buffer	[_,_,_,_]	[5,_,_,_]	[5,9,_,_]	[5,9,_,_]	[5,9,3,_]	[5,9,3,_]	[5,9,3,7]	[5,9,3,7]	[5,9,3,7]	[5,9,3,7]	[2,9,3,7]	[2,9,3,7]	[2,9,3,7]

Key Moments - 3 Insights

Why does the write pointer wrap back to 0 after reaching the buffer size?

Because the buffer is circular, the write pointer resets to 0 to reuse buffer space, as shown in steps 7 and 9 in the execution_table.

How do we know when the buffer is full or empty?

The full flag is set when the write pointer is one position behind the read pointer (step 7), and empty flag is set when both pointers are equal and no data is available (step 10).

Why can't we write data when the buffer is full?

Writing when full would overwrite unread data, so the design waits until space is available, as shown by the full flag in step 7 blocking writes.

Visual Quiz - 3 Questions

Look at the execution_table at step 7, what is the value of the full flag?

A 0

B 1

C -

D Undefined

💡 Hint

Refer to the 'Full Flag' column in execution_table row 7.

At which step does the read pointer wrap back to 0?

A Step 6

B Step 8

C Step 9

D Step 10

💡 Hint

Check the 'Read Pointer' column in execution_table rows 8 and 9.

If we remove the check for full before writing, what would happen?

A Data would be lost by overwriting unread data

B Buffer would never be full

C Read pointer would move incorrectly

D Write pointer would stop incrementing

💡 Hint

Refer to key_moments explanation about full condition preventing overwriting.

Concept Snapshot

FIFO Buffer Design Concept in Verilog:
- Uses circular buffer with read and write pointers
- Write allowed only if buffer not full
- Read allowed only if buffer not empty
- Full when write pointer is one behind read pointer
- Empty when pointers are equal
- Pointers wrap around buffer size

Full Transcript

This visual execution trace shows how a FIFO buffer works in Verilog. It starts with pointers at zero and empty buffer. When write enable is active and buffer is not full, data is written at the write pointer position and the pointer advances. When read enable is active and buffer is not empty, data is read from the read pointer position and the pointer advances. The buffer is circular, so pointers wrap around. The full flag is set when the buffer is full to prevent overwriting unread data. The empty flag is set when no data is available to read. This trace demonstrates pointer updates, buffer content changes, and flag settings step-by-step, helping beginners understand FIFO operation clearly.