FIFO buffer design concept in Verilog - Mini Project: Build & Apply

FIFO Buffer Design Concept

📖 Scenario: You are designing a simple FIFO (First-In-First-Out) buffer in hardware using Verilog. This buffer will store 4-bit data values and allow writing and reading in order.

🎯 Goal: Build a FIFO buffer module with a 4-element storage array, write and read pointers, and logic to write data, read data, and track empty/full status.

📋 What You'll Learn

Create a 4-element register array called fifo_mem to store 4-bit data

Create 2-bit write pointer wr_ptr and read pointer rd_ptr

Create logic to write data into fifo_mem at wr_ptr when write_en is high

Create logic to read data from fifo_mem at rd_ptr when read_en is high

Create signals empty and full to indicate FIFO status

Print the FIFO output data in the final step

💡 Why This Matters

🌍 Real World

FIFO buffers are used in hardware to temporarily store data between components running at different speeds, like in communication interfaces or data processing pipelines.

💼 Career

Understanding FIFO design is important for hardware engineers working on digital design, FPGA programming, and embedded systems.

1

Create FIFO memory and pointers

Create a 4-element register array called fifo_mem to store 4-bit data. Also create 2-bit registers wr_ptr and rd_ptr initialized to 0.

Verilog

reg [3:0] fifo_mem [3:0];
reg [1:0] wr_ptr = 0;
reg [1:0] rd_ptr = 0;
// Your code here

Need a hint?

Use reg [3:0] fifo_mem [3:0]; to create the memory array and reg [1:0] wr_ptr = 0; and rd_ptr for pointers.

2

Add write enable and read enable signals

Add input signals write_en, read_en, and 4-bit input data_in. Also add 4-bit output data_out to read data from FIFO.

Verilog

module fifo_buffer(input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  // Your code here
endmodule

Need a hint?

Declare inputs and outputs in the module header.

3

Implement write and read logic

Inside an always block triggered on clock's positive edge, write data_in to fifo_mem[wr_ptr] and increment wr_ptr when write_en is high. Also read from fifo_mem[rd_ptr] to data_out and increment rd_ptr when read_en is high.

Verilog

module fifo_buffer(input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  always @(posedge clk) begin
    // Your code here
  end
endmodule

Need a hint?

Use non-blocking assignments inside always @(posedge clk) to update memory and pointers.

4

Add empty and full signals and print output

Add empty and full output signals that are high when FIFO is empty or full. Then add a testbench that writes 3 values and reads 2 values, printing data_out after each read.

Verilog

module fifo_buffer(input clk, input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out, output empty, output full);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  // Your code here
endmodule

// Testbench code
// Your code here

Need a hint?

Use assign empty = (wr_ptr == rd_ptr); and assign full = ((wr_ptr + 1) == rd_ptr); to track FIFO status. In the testbench, toggle clk and use $display to print data_out.