FIFO buffer design concept in Verilog - Mini Project: Build & Apply

FIFO Buffer Design Concept

📖 Scenario: You are designing a simple FIFO (First-In-First-Out) buffer in hardware using Verilog. This buffer will store 4-bit data values and allow writing and reading in order.

🎯 Goal: Build a FIFO buffer module with a 4-element storage array, write and read pointers, and logic to write data, read data, and track empty/full status.

📋 What You'll Learn

Create a 4-element register array called fifo_mem to store 4-bit data

Create 2-bit write pointer wr_ptr and read pointer rd_ptr

Create logic to write data into fifo_mem at wr_ptr when write_en is high

Create logic to read data from fifo_mem at rd_ptr when read_en is high

Create signals empty and full to indicate FIFO status

Print the FIFO output data in the final step

💡 Why This Matters

🌍 Real World

FIFO buffers are used in hardware to temporarily store data between components running at different speeds, like in communication interfaces or data processing pipelines.

💼 Career

Understanding FIFO design is important for hardware engineers working on digital design, FPGA programming, and embedded systems.

1

Create FIFO memory and pointers

Create a 4-element register array called fifo_mem to store 4-bit data. Also create 2-bit registers wr_ptr and rd_ptr initialized to 0.

Verilog

reg [3:0] fifo_mem [3:0];
reg [1:0] wr_ptr = 0;
reg [1:0] rd_ptr = 0;
// Your code here

Hint

Use reg [3:0] fifo_mem [3:0]; to create the memory array and reg [1:0] wr_ptr = 0; and rd_ptr for pointers.

2

Add write enable and read enable signals

Add input signals write_en, read_en, and 4-bit input data_in. Also add 4-bit output data_out to read data from FIFO.

Verilog

module fifo_buffer(input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  // Your code here
endmodule

Hint

Declare inputs and outputs in the module header.

3

Implement write and read logic

Inside an always block triggered on clock's positive edge, write data_in to fifo_mem[wr_ptr] and increment wr_ptr when write_en is high. Also read from fifo_mem[rd_ptr] to data_out and increment rd_ptr when read_en is high.

Verilog

module fifo_buffer(input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  always @(posedge clk) begin
    // Your code here
  end
endmodule

Hint

Use non-blocking assignments inside always @(posedge clk) to update memory and pointers.

4

Add empty and full signals and print output

Add empty and full output signals that are high when FIFO is empty or full. Then add a testbench that writes 3 values and reads 2 values, printing data_out after each read.

Verilog

module fifo_buffer(input clk, input write_en, input read_en, input [3:0] data_in, output reg [3:0] data_out, output empty, output full);
  reg [3:0] fifo_mem [3:0];
  reg [1:0] wr_ptr = 0;
  reg [1:0] rd_ptr = 0;
  // Your code here
endmodule

// Testbench code
// Your code here

Hint

Use assign empty = (wr_ptr == rd_ptr); and assign full = ((wr_ptr + 1) == rd_ptr); to track FIFO status. In the testbench, toggle clk and use $display to print data_out.

Practice

1. What is the main purpose of a FIFO buffer in Verilog designs?

easy

A. To perform arithmetic operations on data

B. To store data randomly and output in reverse order

C. To store data in the order it arrives and output it in the same order

D. To compress data before storage

Solution

1. Step 1: Understand FIFO behavior

   A FIFO (First-In-First-Out) buffer stores data in the order it arrives and outputs it in the same order, preserving sequence.

2. Step 2: Compare options

   Options A, B, and D describe behaviors unrelated to FIFO buffers.

3. Final Answer:

   To store data in the order it arrives and output it in the same order -> Option C

4. Quick Check:

   FIFO = First-In-First-Out [OK]

Hint: FIFO means first data in is first data out [OK]

Common Mistakes:

• Confusing FIFO with LIFO (stack)
• Thinking FIFO changes data order
• Assuming FIFO compresses data

2. Which of the following is the correct Verilog syntax to declare a FIFO memory array of 16 elements, each 8 bits wide?

easy

A. wire [7:0] fifo_mem [15:0];

B. reg [7:0] fifo_mem [0:15];

C. reg fifo_mem [7:0] [0:15];

D. wire [15:0] fifo_mem [7:0];

Solution

1. Step 1: Understand Verilog array declaration

   To declare a memory array of 16 elements each 8 bits wide, use reg [7:0] fifo_mem [0:15]; where [7:0] is the bit width and [0:15] is the index range.

2. Step 2: Check options

   reg [7:0] fifo_mem [0:15]; matches the correct syntax. Options A, B, and C have incorrect bit widths or array dimensions.

3. Final Answer:

   reg [7:0] fifo_mem [0:15]; -> Option B

4. Quick Check:

   Memory array = reg [bit_width] name [index_range] [OK]

Hint: Declare memory as reg [width-1:0] name [size-1:0] [OK]

Common Mistakes:

• Swapping bit width and array size
• Using wire instead of reg for memory
• Incorrect array dimension order

3. Given this simplified FIFO write pointer update code snippet in Verilog:

always @(posedge clk) begin
  if (write_enable && !full) begin
    write_ptr <= (write_ptr + 1) % 8;
  end
end

What will be the value of write_ptr after 10 write cycles starting from 0, assuming full is always 0?

medium

A. 10

B. 7

C. 0

D. 2

Solution

1. Step 1: Understand pointer increment with modulo

   The write pointer increments by 1 each cycle and wraps around modulo 8, so it cycles through 0 to 7 repeatedly.

2. Step 2: Calculate pointer after 10 increments

   Starting at 0, after 10 increments: (0 + 10) % 8 = 2.

3. Final Answer:

   2 -> Option D

4. Quick Check:

   (0 + 10) mod 8 = 2 [OK]

Hint: Use modulo to find pointer wrap-around [OK]

Common Mistakes:

• Ignoring modulo wrap-around
• Assuming pointer grows beyond size
• Confusing write and read pointers

4. Identify the error in this FIFO read pointer update code snippet:

always @(posedge clk) begin
  if (read_enable && !empty) begin
    read_ptr = read_ptr + 1;
  end
end

medium

A. Using blocking assignment (=) instead of non-blocking (<=) inside always block

B. Missing reset condition for read_ptr

C. Not checking full signal before increment

D. Using read_enable instead of write_enable

Solution

1. Step 1: Check assignment type in sequential always block

   Inside an always @(posedge clk) block, non-blocking assignment (<=) should be used to update registers to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignment (=), which is incorrect for sequential logic.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option A

4. Quick Check:

   Sequential logic uses <=, not = [OK]

Hint: Use <= for registers in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Forgetting to reset pointers
• Confusing full and empty signals

5. You want to design a FIFO buffer with depth 4 and 8-bit data width in Verilog. Which of the following correctly describes how to detect the FIFO full condition using write and read pointers write_ptr and read_ptr?

hard

A. FIFO is full when (write_ptr + 1) % 4 == read_ptr

B. FIFO is full when write_ptr == read_ptr

C. FIFO is full when write_ptr == (read_ptr + 1) % 8

D. FIFO is full when write_ptr > read_ptr

Solution

1. Step 1: Understand FIFO full condition logic

   In a circular FIFO, the buffer is full when the write pointer is one position behind the read pointer, considering wrap-around.

2. Step 2: Apply modulo with depth 4

   So, full condition is when (write_ptr + 1) % 4 == read_ptr.

3. Final Answer:

   FIFO is full when (write_ptr + 1) % 4 == read_ptr -> Option A

4. Quick Check:

   Full = next write_ptr equals read_ptr [OK]

Hint: Full when next write_ptr equals read_ptr [OK]

Common Mistakes:

• Confusing full with empty condition
• Using wrong modulo base
• Checking write_ptr > read_ptr without wrap