FIFO buffer design concept in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this FIFO write pointer update?

Given a 4-bit write pointer in a FIFO buffer that increments on each write and wraps around, what is the value of the write pointer after 17 writes starting from 0?

Verilog

reg [3:0] write_ptr = 4'b0000;
always @(posedge clk) begin
  if (write_enable) begin
    write_ptr <= write_ptr + 1'b1;
  end
end
// After 17 writes, what is write_ptr?

A 1

B 0

C 17

D 16

💡 Hint

Remember the pointer is 4 bits and wraps around after 15.

The 4-bit pointer counts from 0 to 15, then wraps to 0. After 16 increments, it returns to 0. After 17 increments, it is 1.

🧠 Conceptual

intermediate

Which signal indicates FIFO full condition in a circular buffer?

In a FIFO implemented with read and write pointers, which condition correctly indicates the FIFO is full?

A write_ptr == read_ptr

B read_ptr + 1 == write_ptr (mod buffer size)

C write_ptr > read_ptr

D write_ptr + 1 == read_ptr (mod buffer size)

💡 Hint

Full means next write would overwrite unread data.

The FIFO is full when the write pointer is one position behind the read pointer in a circular buffer, meaning write_ptr + 1 == read_ptr modulo buffer size.

🔧 Debug

advanced

What error does this FIFO read pointer update cause?

Consider this Verilog snippet for FIFO read pointer update. What error will occur?

Verilog

reg [3:0] read_ptr = 4'b0000;
always @(posedge clk) begin
  if (read_enable) begin
    read_ptr <= read_ptr - 1'b1;
  end
end

A Logic error: read_ptr decrements instead of increments

B No error, pointer decrements correctly

C Syntax error: missing semicolon

D Overflow: read_ptr exceeds max value

💡 Hint

Pointers should wrap forward, not backward.

Decrementing the read pointer is incorrect for FIFO implementations. Standard FIFO read pointers increment on read and wrap around using modulo buffer size arithmetic.

📝 Syntax

advanced

Which option correctly declares a FIFO memory array in Verilog?

Select the correct Verilog syntax to declare a FIFO memory of 16 elements, each 8 bits wide.

A reg fifo_mem [7:0] [0:15];

B reg [7:0] fifo_mem [0:15];

C reg [0:15] fifo_mem [7:0];

D reg [7:0] fifo_mem (15 downto 0);

💡 Hint

Memory arrays use reg [width-1:0] name [index range];

Option B correctly declares a 16-element array with 8-bit wide elements. Other options have invalid syntax.

🚀 Application

expert

How many items can this FIFO hold before full?

A FIFO uses 5-bit read and write pointers with full condition defined as (write_ptr + 1) % 32 == read_ptr. How many data items can it hold?

A 30

B 32

C 31

D 16

💡 Hint

Full condition leaves one slot unused to distinguish full from empty.

With 5-bit pointers, buffer size is 32. One slot is reserved to differentiate full and empty, so max data items is 31.