FIFO buffer design concept in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this FIFO write pointer update?

Given a 4-bit write pointer in a FIFO buffer that increments on each write and wraps around, what is the value of the write pointer after 17 writes starting from 0?

Verilog

reg [3:0] write_ptr = 4'b0000;
always @(posedge clk) begin
  if (write_enable) begin
    write_ptr <= write_ptr + 1'b1;
  end
end
// After 17 writes, what is write_ptr?

A 1

B 0

C 17

D 16

💡 Hint

Remember the pointer is 4 bits and wraps around after 15.

The 4-bit pointer counts from 0 to 15, then wraps to 0. After 16 increments, it returns to 0. After 17 increments, it is 1.

🧠 Conceptual

intermediate

Which signal indicates FIFO full condition in a circular buffer?

In a FIFO implemented with read and write pointers, which condition correctly indicates the FIFO is full?

A write_ptr == read_ptr

B read_ptr + 1 == write_ptr (mod buffer size)

C write_ptr > read_ptr

D write_ptr + 1 == read_ptr (mod buffer size)

💡 Hint

Full means next write would overwrite unread data.

The FIFO is full when the write pointer is one position behind the read pointer in a circular buffer, meaning write_ptr + 1 == read_ptr modulo buffer size.

🔧 Debug

advanced

What error does this FIFO read pointer update cause?

Consider this Verilog snippet for FIFO read pointer update. What error will occur?

Verilog

reg [3:0] read_ptr = 4'b0000;
always @(posedge clk) begin
  if (read_enable) begin
    read_ptr <= read_ptr - 1'b1;
  end
end

A Logic error: read_ptr decrements instead of increments

B No error, pointer decrements correctly

C Syntax error: missing semicolon

D Overflow: read_ptr exceeds max value

💡 Hint

Pointers should wrap forward, not backward.

Decrementing the read pointer is incorrect for FIFO implementations. Standard FIFO read pointers increment on read and wrap around using modulo buffer size arithmetic.

📝 Syntax

advanced

Which option correctly declares a FIFO memory array in Verilog?

Select the correct Verilog syntax to declare a FIFO memory of 16 elements, each 8 bits wide.

A reg fifo_mem [7:0] [0:15];

B reg [7:0] fifo_mem [0:15];

C reg [0:15] fifo_mem [7:0];

D reg [7:0] fifo_mem (15 downto 0);

💡 Hint

Memory arrays use reg [width-1:0] name [index range];

Option B correctly declares a 16-element array with 8-bit wide elements. Other options have invalid syntax.

🚀 Application

expert

How many items can this FIFO hold before full?

A FIFO uses 5-bit read and write pointers with full condition defined as (write_ptr + 1) % 32 == read_ptr. How many data items can it hold?

A 30

B 32

C 31

D 16

💡 Hint

Full condition leaves one slot unused to distinguish full from empty.

With 5-bit pointers, buffer size is 32. One slot is reserved to differentiate full and empty, so max data items is 31.

Practice

1. What is the main purpose of a FIFO buffer in Verilog designs?

easy

A. To perform arithmetic operations on data

B. To store data randomly and output in reverse order

C. To store data in the order it arrives and output it in the same order

D. To compress data before storage

Solution

1. Step 1: Understand FIFO behavior

   A FIFO (First-In-First-Out) buffer stores data in the order it arrives and outputs it in the same order, preserving sequence.

2. Step 2: Compare options

   Options A, B, and D describe behaviors unrelated to FIFO buffers.

3. Final Answer:

   To store data in the order it arrives and output it in the same order -> Option C

4. Quick Check:

   FIFO = First-In-First-Out [OK]

Hint: FIFO means first data in is first data out [OK]

Common Mistakes:

• Confusing FIFO with LIFO (stack)
• Thinking FIFO changes data order
• Assuming FIFO compresses data

2. Which of the following is the correct Verilog syntax to declare a FIFO memory array of 16 elements, each 8 bits wide?

easy

A. wire [7:0] fifo_mem [15:0];

B. reg [7:0] fifo_mem [0:15];

C. reg fifo_mem [7:0] [0:15];

D. wire [15:0] fifo_mem [7:0];

Solution

1. Step 1: Understand Verilog array declaration

   To declare a memory array of 16 elements each 8 bits wide, use reg [7:0] fifo_mem [0:15]; where [7:0] is the bit width and [0:15] is the index range.

2. Step 2: Check options

   reg [7:0] fifo_mem [0:15]; matches the correct syntax. Options A, B, and C have incorrect bit widths or array dimensions.

3. Final Answer:

   reg [7:0] fifo_mem [0:15]; -> Option B

4. Quick Check:

   Memory array = reg [bit_width] name [index_range] [OK]

Hint: Declare memory as reg [width-1:0] name [size-1:0] [OK]

Common Mistakes:

• Swapping bit width and array size
• Using wire instead of reg for memory
• Incorrect array dimension order

3. Given this simplified FIFO write pointer update code snippet in Verilog:

always @(posedge clk) begin
  if (write_enable && !full) begin
    write_ptr <= (write_ptr + 1) % 8;
  end
end

What will be the value of write_ptr after 10 write cycles starting from 0, assuming full is always 0?

medium

A. 10

B. 7

C. 0

D. 2

Solution

1. Step 1: Understand pointer increment with modulo

   The write pointer increments by 1 each cycle and wraps around modulo 8, so it cycles through 0 to 7 repeatedly.

2. Step 2: Calculate pointer after 10 increments

   Starting at 0, after 10 increments: (0 + 10) % 8 = 2.

3. Final Answer:

   2 -> Option D

4. Quick Check:

   (0 + 10) mod 8 = 2 [OK]

Hint: Use modulo to find pointer wrap-around [OK]

Common Mistakes:

• Ignoring modulo wrap-around
• Assuming pointer grows beyond size
• Confusing write and read pointers

4. Identify the error in this FIFO read pointer update code snippet:

always @(posedge clk) begin
  if (read_enable && !empty) begin
    read_ptr = read_ptr + 1;
  end
end

medium

A. Using blocking assignment (=) instead of non-blocking (<=) inside always block

B. Missing reset condition for read_ptr

C. Not checking full signal before increment

D. Using read_enable instead of write_enable

Solution

1. Step 1: Check assignment type in sequential always block

   Inside an always @(posedge clk) block, non-blocking assignment (<=) should be used to update registers to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignment (=), which is incorrect for sequential logic.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option A

4. Quick Check:

   Sequential logic uses <=, not = [OK]

Hint: Use <= for registers in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Forgetting to reset pointers
• Confusing full and empty signals

5. You want to design a FIFO buffer with depth 4 and 8-bit data width in Verilog. Which of the following correctly describes how to detect the FIFO full condition using write and read pointers write_ptr and read_ptr?

hard

A. FIFO is full when (write_ptr + 1) % 4 == read_ptr

B. FIFO is full when write_ptr == read_ptr

C. FIFO is full when write_ptr == (read_ptr + 1) % 8

D. FIFO is full when write_ptr > read_ptr

Solution

1. Step 1: Understand FIFO full condition logic

   In a circular FIFO, the buffer is full when the write pointer is one position behind the read pointer, considering wrap-around.

2. Step 2: Apply modulo with depth 4

   So, full condition is when (write_ptr + 1) % 4 == read_ptr.

3. Final Answer:

   FIFO is full when (write_ptr + 1) % 4 == read_ptr -> Option A

4. Quick Check:

   Full = next write_ptr equals read_ptr [OK]

Hint: Full when next write_ptr equals read_ptr [OK]

Common Mistakes:

• Confusing full with empty condition
• Using wrong modulo base
• Checking write_ptr > read_ptr without wrap