Dual-port RAM design in Verilog - Step-by-Step Execution

Concept Flow - Dual-port RAM design

Start

↓

Receive write address, data, write enable

↓

If write enable is 1?

No→Skip write

|Yes↓

Write data to memory at write address

↓

Receive read address

↓

Read data from memory at read address

↓

Output read data

↓

Repeat for next clock cycle

The dual-port RAM allows simultaneous read and write operations on separate ports controlled by clock cycles.

Execution Sample

Verilog

module dual_port_ram(
  input clk,
  input we,
  input [3:0] write_addr,
  input [7:0] write_data,
  input [3:0] read_addr,
  output reg [7:0] read_data
);

  reg [7:0] ram [0:15];

  always @(posedge clk) begin
    if (we) begin
      ram[write_addr] <= write_data;
    end
    read_data <= ram[read_addr];
  end

endmodule

This code defines a dual-port RAM with separate read and write addresses and data lines.

Execution Table

Step	clk	we	write_addr	write_data	read_addr	Memory State	read_data	Action
1	0	0	0000	00000000	0000	[All zeros]	00000000	Initial state, no write, read outputs 0
2	1	1	0010	10101010	0000	[Addr 2=10101010]	00000000	Write data 0xAA at address 2, read address 0 outputs 0
3	0	0	0010	10101010	0010	[Addr 2=10101010]	10101010	No write, read from address 2 outputs 0xAA
4	1	1	0001	11110000	0010	[Addr 1=11110000, Addr 2=10101010]	10101010	Write 0xF0 at address 1, read address 2 outputs 0xAA
5	0	0	0001	11110000	0001	[Addr 1=11110000, Addr 2=10101010]	11110000	No write, read from address 1 outputs 0xF0
6	1	0	0000	00000000	0011	[Addr 1=11110000, Addr 2=10101010]	00000000	No write, read from address 3 outputs 0
7	End	-	-	-	-	-	-	Simulation ends

💡 Simulation ends after several clock cycles demonstrating read and write operations.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
clk	0	1	0	1	0	1	End
we	0	1	0	1	0	0	-
write_addr	0000	0010	0010	0001	0001	0000	-
write_data	00000000	10101010	10101010	11110000	11110000	00000000	-
read_addr	0000	0000	0010	0010	0001	0011	-
read_data	00000000	00000000	10101010	10101010	11110000	00000000	-
Memory	[All zeros]	[Addr 2=10101010]	[Addr 2=10101010]	[Addr 1=11110000, Addr 2=10101010]	[Addr 1=11110000, Addr 2=10101010]	[Addr 1=11110000, Addr 2=10101010]	-

Key Moments - 3 Insights

Why does the read_data output the old value immediately after a write?

Because the read happens in the same clock cycle but before the write updates memory, so read_data shows the previous value as seen in steps 2 and 3.

Can the write and read addresses be the same at the same time?

Yes, but the read will output the old data before the write updates memory in that clock cycle, as shown in step 4 and 5.

What happens if write enable (we) is 0?

No write occurs; memory stays unchanged and read outputs data from the read address, as in steps 1, 3, 5, and 6.

Visual Quiz - 3 Questions

Look at the execution table at step 3, what is the value of read_data?

A 10101010

B 00000000

C 11110000

D Undefined

💡 Hint

Check the 'read_data' column at step 3 in the execution_table.

At which step does the memory first get written with 11110000?

A Step 2

B Step 4

C Step 5

D Step 6

💡 Hint

Look at the 'Memory State' column to see when Addr 1 changes.

If write enable (we) was always 0, what would happen to memory?

A Memory would update every clock cycle

B Memory would only update on read

C Memory would never change from initial zeros

D Memory would randomly change

💡 Hint

Refer to the 'we' column and memory changes in the execution_table.

Concept Snapshot

Dual-port RAM allows simultaneous read and write.
Write port uses write address, data, and write enable.
Read port uses read address to output data.
Writes happen on clock edge if enabled.
Reads output data from memory at read address.
Read and write ports operate independently.

Full Transcript

This visual execution trace shows how a dual-port RAM works in Verilog. The RAM has separate ports for reading and writing. On each clock cycle, if write enable is high, data is written to the memory at the write address. Simultaneously, data is read from the memory at the read address and output. The trace shows step-by-step how the clock, write enable, addresses, and data change, and how memory updates and read data outputs respond. Key moments clarify why read data shows old values immediately after writes and how write enable controls memory updates. The quiz tests understanding of memory state and outputs at different steps. The snapshot summarizes the dual-port RAM behavior and usage.

Practice

1. What is the main advantage of using a dual-port RAM in hardware design?

easy

A. It allows two independent read/write operations simultaneously.

B. It reduces the size of the memory.

C. It makes the RAM slower but cheaper.

D. It only supports read operations.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM has two ports that can access memory independently at the same time.

2. Step 2: Identify the main benefit

   This allows simultaneous read/write operations, improving performance.

3. Final Answer:

   It allows two independent read/write operations simultaneously. -> Option A

4. Quick Check:

   Dual-port RAM = two simultaneous accesses [OK]

Hint: Dual-port RAM means two ports can access memory at once [OK]

Common Mistakes:

• Thinking it reduces memory size
• Assuming it only supports reads
• Believing it slows down RAM

2. Which of the following is the correct Verilog port declaration for a dual-port RAM with separate read and write ports?

easy

A. input clk, input [7:0] addr_a, output [7:0] data_out_a, input [7:0] addr_b, output [7:0] data_out_b;

B. input clk, input [7:0] addr, input [7:0] data_in, output [7:0] data_out, input we;

C. input clk, input [7:0] addr, output [7:0] data_out, input we, input re;

D. input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b;

Solution

1. Step 1: Identify dual-port RAM ports

   Dual-port RAM needs separate address, data, and write enable signals for each port.

2. Step 2: Match correct declaration

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; declares separate addr, data_in, data_out, and we signals for ports A and B, matching dual-port RAM design.

3. Final Answer:

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; -> Option D

4. Quick Check:

   Separate signals per port = input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; [OK]

Hint: Dual-port RAM needs separate signals for each port [OK]

Common Mistakes:

• Using single address and data signals for both ports
• Missing write enable signals
• Confusing read and write signals

3. Given the following Verilog snippet for a dual-port RAM, what will be the value of data_out_b after the clock edge if we_b is 0 and addr_b is 3?

reg [7:0] ram [0:7];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

medium

A. The value of data_in_b.

B. The value stored at address 3 before the clock edge.

C. Zero, because we_b is 0.

D. Undefined, because data_out_b is not assigned.

Solution

1. Step 1: Understand write enable effect

   Since we_b is 0, no write occurs at addr_b on this clock edge.

2. Step 2: Determine data_out_b value

   data_out_b reads the RAM at addr_b, so it outputs the stored value at address 3 before the clock edge.

3. Final Answer:

   The value stored at address 3 before the clock edge. -> Option B

4. Quick Check:

   we_b=0 means no write; output = stored value [OK]

Hint: If write enable is 0, output shows stored memory value [OK]

Common Mistakes:

• Assuming data_out_b equals data_in_b always
• Thinking output is zero when no write
• Ignoring read operation on clock edge

4. Identify the error in this dual-port RAM Verilog code snippet:

reg [7:0] ram [0:15];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

assign data_out_a = ram[addr_a];

medium

A. Conflicting assignments to data_out_a: both procedural and continuous.

B. Missing clock signal in sensitivity list.

C. Incorrect RAM size declaration.

D. No write enable signals declared.

Solution

1. Step 1: Check assignments to data_out_a

   Data_out_a is assigned inside the always block and also by continuous assign statement, causing conflict.

2. Step 2: Understand Verilog rules

   A signal cannot be driven by both procedural and continuous assignments simultaneously.

3. Final Answer:

   Conflicting assignments to data_out_a: both procedural and continuous. -> Option A

4. Quick Check:

   Signal driven twice = conflict error [OK]

Hint: Avoid assigning same signal in always block and assign statement [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking sensitivity list needs clock and addr
• Misunderstanding RAM size syntax

5. You want to design a dual-port RAM where Port A is write-only and Port B is read-only. Which modification correctly implements this behavior in Verilog?

hard

A. Disable clock on Port B to make it read-only.

B. Use write enable on both ports and read data from both ports.

C. Use write enable only on Port A and never write on Port B; read data only from Port B.

D. Use a single write enable for both ports.

Solution

1. Step 1: Define port roles

   Port A should only write data, so it needs a write enable and no read output.

2. Step 2: Configure Port B as read-only

   Port B should not write, so write enable is never asserted; it only reads data from RAM.

3. Final Answer:

   Use write enable only on Port A and never write on Port B; read data only from Port B. -> Option C

4. Quick Check:

   Write-only Port A + Read-only Port B = Use write enable only on Port A and never write on Port B; read data only from Port B. [OK]

Hint: Assign write enable only to write port, read from the other [OK]

Common Mistakes:

• Trying to write on both ports
• Disabling clock to control read/write
• Using single write enable for both ports