Dual-port RAM design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a dual-port RAM module with clock and reset inputs.

Verilog

module dual_port_ram(
    input wire clk,
    input wire rst,
    input wire [3:0] addr_a,
    input wire [3:0] addr_b,
    input wire [7:0] data_in_a,
    output reg [7:0] data_out_b
);

    reg [7:0] ram [0:15];

    always @(posedge [1]) begin
        if (rst) begin
            // reset logic
        end
    end

endmodule

Drag options to blanks, or click blank then click option'

Aaddr_a

Bdata_in_a

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset signal instead of clock in the always block sensitivity list.

Using data or address signals instead of clock.

The always block is triggered on the positive edge of the clock signal 'clk'.

2fill in blank

medium

Complete the code to write data to port A of the RAM on the clock edge.

Verilog

always @(posedge clk) begin
    if (write_enable) begin
        ram[[1]] <= data_in_a;
    end
end

Drag options to blanks, or click blank then click option'

Aaddr_a

Baddr_b

Cdata_out_b

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using the wrong address signal for writing data.

Using output signals as address.

Data is written to the RAM at the address specified by 'addr_a' on port A.

3fill in blank

hard

Fix the error in the read logic for port B to output data correctly.

Verilog

always @(posedge clk) begin
    data_out_b <= ram[[1]];
end

Drag options to blanks, or click blank then click option'

Aaddr_a

Baddr_b

Cdata_in_a

Dwrite_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using port A address for reading port B data.

Using data input signals as address.

Port B reads data from the RAM at the address 'addr_b'.

4fill in blank

hard

Fill both blanks to complete the conditional write logic with write enable and reset.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        ram[addr_a] <= data_in_a;
    end else if ([2]) begin
        // reset RAM contents
    end
end

Drag options to blanks, or click blank then click option'

Awrite_enable

Bclk

Crst

Ddata_out_b

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing clock with write enable or reset signals.

Using output signals in conditions.

Write occurs when 'write_enable' is high; reset logic triggers when 'rst' is high.

5fill in blank

hard

Fill all three blanks to complete the dual-port RAM read and write operations with enable signals.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        ram[addr_a] <= data_in_a;
    end
    if ([2]) begin
        data_out_b <= ram[[3]];
    end
end

Drag options to blanks, or click blank then click option'

Awrite_enable

Bread_enable

Caddr_b

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up write and read enable signals.

Using wrong address for reading.

Write occurs when 'write_enable' is high; read occurs when 'read_enable' is high, reading from 'addr_b'.

Practice

1. What is the main advantage of using a dual-port RAM in hardware design?

easy

A. It allows two independent read/write operations simultaneously.

B. It reduces the size of the memory.

C. It makes the RAM slower but cheaper.

D. It only supports read operations.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM has two ports that can access memory independently at the same time.

2. Step 2: Identify the main benefit

   This allows simultaneous read/write operations, improving performance.

3. Final Answer:

   It allows two independent read/write operations simultaneously. -> Option A

4. Quick Check:

   Dual-port RAM = two simultaneous accesses [OK]

Hint: Dual-port RAM means two ports can access memory at once [OK]

Common Mistakes:

• Thinking it reduces memory size
• Assuming it only supports reads
• Believing it slows down RAM

2. Which of the following is the correct Verilog port declaration for a dual-port RAM with separate read and write ports?

easy

A. input clk, input [7:0] addr_a, output [7:0] data_out_a, input [7:0] addr_b, output [7:0] data_out_b;

B. input clk, input [7:0] addr, input [7:0] data_in, output [7:0] data_out, input we;

C. input clk, input [7:0] addr, output [7:0] data_out, input we, input re;

D. input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b;

Solution

1. Step 1: Identify dual-port RAM ports

   Dual-port RAM needs separate address, data, and write enable signals for each port.

2. Step 2: Match correct declaration

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; declares separate addr, data_in, data_out, and we signals for ports A and B, matching dual-port RAM design.

3. Final Answer:

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; -> Option D

4. Quick Check:

   Separate signals per port = input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; [OK]

Hint: Dual-port RAM needs separate signals for each port [OK]

Common Mistakes:

• Using single address and data signals for both ports
• Missing write enable signals
• Confusing read and write signals

3. Given the following Verilog snippet for a dual-port RAM, what will be the value of data_out_b after the clock edge if we_b is 0 and addr_b is 3?

reg [7:0] ram [0:7];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

medium

A. The value of data_in_b.

B. The value stored at address 3 before the clock edge.

C. Zero, because we_b is 0.

D. Undefined, because data_out_b is not assigned.

Solution

1. Step 1: Understand write enable effect

   Since we_b is 0, no write occurs at addr_b on this clock edge.

2. Step 2: Determine data_out_b value

   data_out_b reads the RAM at addr_b, so it outputs the stored value at address 3 before the clock edge.

3. Final Answer:

   The value stored at address 3 before the clock edge. -> Option B

4. Quick Check:

   we_b=0 means no write; output = stored value [OK]

Hint: If write enable is 0, output shows stored memory value [OK]

Common Mistakes:

• Assuming data_out_b equals data_in_b always
• Thinking output is zero when no write
• Ignoring read operation on clock edge

4. Identify the error in this dual-port RAM Verilog code snippet:

reg [7:0] ram [0:15];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

assign data_out_a = ram[addr_a];

medium

A. Conflicting assignments to data_out_a: both procedural and continuous.

B. Missing clock signal in sensitivity list.

C. Incorrect RAM size declaration.

D. No write enable signals declared.

Solution

1. Step 1: Check assignments to data_out_a

   Data_out_a is assigned inside the always block and also by continuous assign statement, causing conflict.

2. Step 2: Understand Verilog rules

   A signal cannot be driven by both procedural and continuous assignments simultaneously.

3. Final Answer:

   Conflicting assignments to data_out_a: both procedural and continuous. -> Option A

4. Quick Check:

   Signal driven twice = conflict error [OK]

Hint: Avoid assigning same signal in always block and assign statement [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking sensitivity list needs clock and addr
• Misunderstanding RAM size syntax

5. You want to design a dual-port RAM where Port A is write-only and Port B is read-only. Which modification correctly implements this behavior in Verilog?

hard

A. Disable clock on Port B to make it read-only.

B. Use write enable on both ports and read data from both ports.

C. Use write enable only on Port A and never write on Port B; read data only from Port B.

D. Use a single write enable for both ports.

Solution

1. Step 1: Define port roles

   Port A should only write data, so it needs a write enable and no read output.

2. Step 2: Configure Port B as read-only

   Port B should not write, so write enable is never asserted; it only reads data from RAM.

3. Final Answer:

   Use write enable only on Port A and never write on Port B; read data only from Port B. -> Option C

4. Quick Check:

   Write-only Port A + Read-only Port B = Use write enable only on Port A and never write on Port B; read data only from Port B. [OK]

Hint: Assign write enable only to write port, read from the other [OK]

Common Mistakes:

• Trying to write on both ports
• Disabling clock to control read/write
• Using single write enable for both ports