Dual-port RAM design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a dual-port RAM module with clock and reset inputs.

Verilog

module dual_port_ram(
    input wire clk,
    input wire rst,
    input wire [3:0] addr_a,
    input wire [3:0] addr_b,
    input wire [7:0] data_in_a,
    output reg [7:0] data_out_b
);

    reg [7:0] ram [0:15];

    always @(posedge [1]) begin
        if (rst) begin
            // reset logic
        end
    end

endmodule

Drag options to blanks, or click blank then click option'

Aaddr_a

Bdata_in_a

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset signal instead of clock in the always block sensitivity list.

Using data or address signals instead of clock.

The always block is triggered on the positive edge of the clock signal 'clk'.

2fill in blank

medium

Complete the code to write data to port A of the RAM on the clock edge.

Verilog

always @(posedge clk) begin
    if (write_enable) begin
        ram[[1]] <= data_in_a;
    end
end

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Aaddr_a

Baddr_b

Cdata_out_b

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using the wrong address signal for writing data.

Using output signals as address.

Data is written to the RAM at the address specified by 'addr_a' on port A.

3fill in blank

hard

Fix the error in the read logic for port B to output data correctly.

Verilog

always @(posedge clk) begin
    data_out_b <= ram[[1]];
end

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Aaddr_a

Baddr_b

Cdata_in_a

Dwrite_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using port A address for reading port B data.

Using data input signals as address.

Port B reads data from the RAM at the address 'addr_b'.

4fill in blank

hard

Fill both blanks to complete the conditional write logic with write enable and reset.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        ram[addr_a] <= data_in_a;
    end else if ([2]) begin
        // reset RAM contents
    end
end

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Awrite_enable

Bclk

Crst

Ddata_out_b

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing clock with write enable or reset signals.

Using output signals in conditions.

Write occurs when 'write_enable' is high; reset logic triggers when 'rst' is high.

5fill in blank

hard

Fill all three blanks to complete the dual-port RAM read and write operations with enable signals.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        ram[addr_a] <= data_in_a;
    end
    if ([2]) begin
        data_out_b <= ram[[3]];
    end
end

Drag options to blanks, or click blank then click option'

Awrite_enable

Bread_enable

Caddr_b

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up write and read enable signals.

Using wrong address for reading.

Write occurs when 'write_enable' is high; read occurs when 'read_enable' is high, reading from 'addr_b'.