Dual-port RAM design in Verilog - Mini Project: Build & Apply

Dual-port RAM design

📖 Scenario: You are designing a simple dual-port RAM module in Verilog. This RAM has two separate ports: one for writing data and one for reading data. This is useful in many digital systems where you want to read and write at the same time without conflicts.

🎯 Goal: Build a dual-port RAM module with separate read and write ports. You will create the memory array, add input signals for addresses and data, implement the write and read logic, and finally display the read data.

📋 What You'll Learn

Create a memory array with 16 locations, each 8 bits wide

Add input signals for write address, write data, write enable, read address

Implement write logic that writes data to memory on the rising clock edge when write enable is high

Implement read logic that outputs data from the read address asynchronously

Display the read data output

💡 Why This Matters

🌍 Real World

Dual-port RAMs are used in digital systems like CPUs and FPGAs to allow simultaneous read and write operations, improving performance.

💼 Career

Understanding dual-port RAM design is important for hardware engineers working on memory design, embedded systems, and FPGA development.

1

Create the memory array

Create a reg array called mem with 16 elements, each 8 bits wide.

Verilog

// Your code here
// Create a reg array called mem with 16 elements of 8 bits each

Hint

Use reg [7:0] mem [0:15]; to declare a memory with 16 locations of 8 bits each.

2

Add input and output signals

Add input signals clk, we (write enable), write_addr (4 bits), write_data (8 bits), and read_addr (4 bits). Add output signal read_data (8 bits).

Verilog

reg [7:0] mem [0:15];
// Declare inputs clk, we, write_addr[3:0], write_data[7:0], read_addr[3:0]
// Declare output read_data[7:0]
// Your code here

Hint

Declare inputs and outputs exactly as input clk;, input we;, input [3:0] write_addr;, input [7:0] write_data;, input [3:0] read_addr;, and output [7:0] read_data;.

3

Implement write and read logic

Write an always @(posedge clk) block that writes write_data to mem[write_addr] when we is high. Assign read_data to mem[read_addr] asynchronously.

Verilog

reg [7:0] mem [0:15];

input clk;
input we;
input [3:0] write_addr;
input [7:0] write_data;
input [3:0] read_addr;
output [7:0] read_data;

// Add always block for writing data on posedge clk when we is high
// Assign read_data to mem at read_addr asynchronously
// Your code here

Hint

Use a clocked always block for writing and a combinational always @(*) block for reading.

4

Display the read data

Write a initial block that sets some values in memory using the write port and then displays the read_data for a given read_addr using $display.

Verilog

reg [7:0] mem [0:15];

input clk;
input we;
input [3:0] write_addr;
input [7:0] write_data;
input [3:0] read_addr;
output reg [7:0] read_data;

always @(posedge clk) begin
    if (we) begin
        mem[write_addr] <= write_data;
    end
end

always @(*) begin
    read_data = mem[read_addr];
end

// Add initial block to write values and display read_data
// Your code here

Hint

Use $display("Read data at address 4: %h", read_data); to show the read data in hex.

Practice

1. What is the main advantage of using a dual-port RAM in hardware design?

easy

A. It allows two independent read/write operations simultaneously.

B. It reduces the size of the memory.

C. It makes the RAM slower but cheaper.

D. It only supports read operations.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM has two ports that can access memory independently at the same time.

2. Step 2: Identify the main benefit

   This allows simultaneous read/write operations, improving performance.

3. Final Answer:

   It allows two independent read/write operations simultaneously. -> Option A

4. Quick Check:

   Dual-port RAM = two simultaneous accesses [OK]

Hint: Dual-port RAM means two ports can access memory at once [OK]

Common Mistakes:

• Thinking it reduces memory size
• Assuming it only supports reads
• Believing it slows down RAM

2. Which of the following is the correct Verilog port declaration for a dual-port RAM with separate read and write ports?

easy

A. input clk, input [7:0] addr_a, output [7:0] data_out_a, input [7:0] addr_b, output [7:0] data_out_b;

B. input clk, input [7:0] addr, input [7:0] data_in, output [7:0] data_out, input we;

C. input clk, input [7:0] addr, output [7:0] data_out, input we, input re;

D. input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b;

Solution

1. Step 1: Identify dual-port RAM ports

   Dual-port RAM needs separate address, data, and write enable signals for each port.

2. Step 2: Match correct declaration

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; declares separate addr, data_in, data_out, and we signals for ports A and B, matching dual-port RAM design.

3. Final Answer:

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; -> Option D

4. Quick Check:

   Separate signals per port = input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; [OK]

Hint: Dual-port RAM needs separate signals for each port [OK]

Common Mistakes:

• Using single address and data signals for both ports
• Missing write enable signals
• Confusing read and write signals

3. Given the following Verilog snippet for a dual-port RAM, what will be the value of data_out_b after the clock edge if we_b is 0 and addr_b is 3?

reg [7:0] ram [0:7];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

medium

A. The value of data_in_b.

B. The value stored at address 3 before the clock edge.

C. Zero, because we_b is 0.

D. Undefined, because data_out_b is not assigned.

Solution

1. Step 1: Understand write enable effect

   Since we_b is 0, no write occurs at addr_b on this clock edge.

2. Step 2: Determine data_out_b value

   data_out_b reads the RAM at addr_b, so it outputs the stored value at address 3 before the clock edge.

3. Final Answer:

   The value stored at address 3 before the clock edge. -> Option B

4. Quick Check:

   we_b=0 means no write; output = stored value [OK]

Hint: If write enable is 0, output shows stored memory value [OK]

Common Mistakes:

• Assuming data_out_b equals data_in_b always
• Thinking output is zero when no write
• Ignoring read operation on clock edge

4. Identify the error in this dual-port RAM Verilog code snippet:

reg [7:0] ram [0:15];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

assign data_out_a = ram[addr_a];

medium

A. Conflicting assignments to data_out_a: both procedural and continuous.

B. Missing clock signal in sensitivity list.

C. Incorrect RAM size declaration.

D. No write enable signals declared.

Solution

1. Step 1: Check assignments to data_out_a

   Data_out_a is assigned inside the always block and also by continuous assign statement, causing conflict.

2. Step 2: Understand Verilog rules

   A signal cannot be driven by both procedural and continuous assignments simultaneously.

3. Final Answer:

   Conflicting assignments to data_out_a: both procedural and continuous. -> Option A

4. Quick Check:

   Signal driven twice = conflict error [OK]

Hint: Avoid assigning same signal in always block and assign statement [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking sensitivity list needs clock and addr
• Misunderstanding RAM size syntax

5. You want to design a dual-port RAM where Port A is write-only and Port B is read-only. Which modification correctly implements this behavior in Verilog?

hard

A. Disable clock on Port B to make it read-only.

B. Use write enable on both ports and read data from both ports.

C. Use write enable only on Port A and never write on Port B; read data only from Port B.

D. Use a single write enable for both ports.

Solution

1. Step 1: Define port roles

   Port A should only write data, so it needs a write enable and no read output.

2. Step 2: Configure Port B as read-only

   Port B should not write, so write enable is never asserted; it only reads data from RAM.

3. Final Answer:

   Use write enable only on Port A and never write on Port B; read data only from Port B. -> Option C

4. Quick Check:

   Write-only Port A + Read-only Port B = Use write enable only on Port A and never write on Port B; read data only from Port B. [OK]

Hint: Assign write enable only to write port, read from the other [OK]

Common Mistakes:

• Trying to write on both ports
• Disabling clock to control read/write
• Using single write enable for both ports