Dual-port RAM design in Verilog - Mini Project: Build & Apply

Dual-port RAM design

📖 Scenario: You are designing a simple dual-port RAM module in Verilog. This RAM has two separate ports: one for writing data and one for reading data. This is useful in many digital systems where you want to read and write at the same time without conflicts.

🎯 Goal: Build a dual-port RAM module with separate read and write ports. You will create the memory array, add input signals for addresses and data, implement the write and read logic, and finally display the read data.

📋 What You'll Learn

Create a memory array with 16 locations, each 8 bits wide

Add input signals for write address, write data, write enable, read address

Implement write logic that writes data to memory on the rising clock edge when write enable is high

Implement read logic that outputs data from the read address asynchronously

Display the read data output

💡 Why This Matters

🌍 Real World

Dual-port RAMs are used in digital systems like CPUs and FPGAs to allow simultaneous read and write operations, improving performance.

💼 Career

Understanding dual-port RAM design is important for hardware engineers working on memory design, embedded systems, and FPGA development.

1

Create the memory array

Create a reg array called mem with 16 elements, each 8 bits wide.

Verilog

// Your code here
// Create a reg array called mem with 16 elements of 8 bits each

Need a hint?

Use reg [7:0] mem [0:15]; to declare a memory with 16 locations of 8 bits each.

2

Add input and output signals

Add input signals clk, we (write enable), write_addr (4 bits), write_data (8 bits), and read_addr (4 bits). Add output signal read_data (8 bits).

Verilog

reg [7:0] mem [0:15];
// Declare inputs clk, we, write_addr[3:0], write_data[7:0], read_addr[3:0]
// Declare output read_data[7:0]
// Your code here

Need a hint?

Declare inputs and outputs exactly as input clk;, input we;, input [3:0] write_addr;, input [7:0] write_data;, input [3:0] read_addr;, and output [7:0] read_data;.

3

Implement write and read logic

Write an always @(posedge clk) block that writes write_data to mem[write_addr] when we is high. Assign read_data to mem[read_addr] asynchronously.

Verilog

reg [7:0] mem [0:15];

input clk;
input we;
input [3:0] write_addr;
input [7:0] write_data;
input [3:0] read_addr;
output [7:0] read_data;

// Add always block for writing data on posedge clk when we is high
// Assign read_data to mem at read_addr asynchronously
// Your code here

Need a hint?

Use a clocked always block for writing and a combinational always @(*) block for reading.

4

Display the read data

Write a initial block that sets some values in memory using the write port and then displays the read_data for a given read_addr using $display.

Verilog

reg [7:0] mem [0:15];

input clk;
input we;
input [3:0] write_addr;
input [7:0] write_data;
input [3:0] read_addr;
output reg [7:0] read_data;

always @(posedge clk) begin
    if (we) begin
        mem[write_addr] <= write_data;
    end
end

always @(*) begin
    read_data = mem[read_addr];
end

// Add initial block to write values and display read_data
// Your code here

Need a hint?

Use $display("Read data at address 4: %h", read_data); to show the read data in hex.