Dual-port RAM design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Dual-Port RAM Write and Read

What is the output of the following Verilog testbench snippet that writes and reads from a dual-port RAM?

Verilog

module dual_port_ram(
  input wire clk,
  input wire we_a, we_b,
  input wire [3:0] addr_a, addr_b,
  input wire [7:0] din_a, din_b,
  output reg [7:0] dout_a, dout_b
);
  reg [7:0] ram [0:15];

  always @(posedge clk) begin
    if (we_a) ram[addr_a] <= din_a;
    dout_a <= ram[addr_a];
  end

  always @(posedge clk) begin
    if (we_b) ram[addr_b] <= din_b;
    dout_b <= ram[addr_b];
  end
endmodule

module testbench;
  reg clk = 0;
  reg we_a, we_b;
  reg [3:0] addr_a, addr_b;
  reg [7:0] din_a, din_b;
  wire [7:0] dout_a, dout_b;

  dual_port_ram ram_inst(clk, we_a, we_b, addr_a, addr_b, din_a, din_b, dout_a, dout_b);

  always #5 clk = ~clk;

  initial begin
    we_a = 1; addr_a = 4'd3; din_a = 8'hAA;
    we_b = 1; addr_b = 4'd3; din_b = 8'h55;
    #10;
    we_a = 0; we_b = 0;
    #10;
    $display("dout_a = %h, dout_b = %h", dout_a, dout_b);
    $finish;
  end
endmodule

A dout_a = 55, dout_b = 55

B dout_a = AA, dout_b = AA

C dout_a = AA, dout_b = 55

D dout_a = 55, dout_b = AA

💡 Hint

Remember that both ports write to the same address on the same clock edge. The order of writes affects the final stored value.

Both ports write to address 3 on the same clock edge. Port B's write happens after Port A's in the code, so the final stored value is 0x55. Both dout_a and dout_b read the updated value 0x55 after the clock edge.

🧠 Conceptual

intermediate

Understanding Dual-Port RAM Read Behavior

In a synchronous dual-port RAM, if both ports read from the same address simultaneously without any write enable active, what will be the output on both ports?

A Both ports output zero regardless of stored data.

B Both ports output the data from the other port's address.

C Both ports output the stored data at that address.

D One port outputs data, the other outputs undefined value.

💡 Hint

Think about how synchronous RAM reads work when no writes occur.

When no write occurs, both ports read the stored data at the requested address. Since both read the same address, both outputs show the stored value.

🔧 Debug

advanced

Identify the Bug in Dual-Port RAM Write Logic

What is the main problem in this dual-port RAM write logic snippet? always @(posedge clk) begin if (we_a) ram[addr_a] <= din_a; else if (we_b) ram[addr_b] <= din_b; end

A The clock edge sensitivity is incorrect.

B Both ports write simultaneously causing data corruption.

C The RAM array is not declared properly.

D Port B's write will never happen if Port A's write enable is true.

💡 Hint

Check how the if-else structure affects port B's write enable.

The else if means port B's write only happens if port A's write enable is false. But if port A's write enable is true, port B's write is skipped. This structure prevents simultaneous writes and may block port B's write incorrectly.

📝 Syntax

advanced

Syntax Error in Dual-Port RAM Declaration

Which option contains the correct syntax to declare a 16x8-bit dual-port RAM array in Verilog?

A reg ram [7:0] [0:15];

B reg [7:0] ram [0:15];

C reg [0:15] ram [7:0];

D reg [7:0] ram [15:0];

💡 Hint

Remember the order: data width first, then address range.

The correct syntax is reg [7:0] ram [0:15]; which means 16 locations (0 to 15) each 8 bits wide. Other options have incorrect dimension order or ranges.

🚀 Application

expert

Number of Unique Data Values Stored After Writes

Given a dual-port RAM with 16 addresses, initially all zero, the following writes occur simultaneously on the same clock edge: - Port A writes 8'h1A to address 5 - Port B writes 8'h2B to address 7 - Port A writes 8'h3C to address 7 - Port B writes 8'h4D to address 5 Assuming the write order in code is Port A then Port B for each port's write, how many unique data values are stored in the RAM after this clock edge?

A 2

B 4

C 1

D 3

💡 Hint

Consider that writes to the same address overwrite each other in order.

Port A writes 0x1A to addr 5, then Port B overwrites addr 5 with 0x4D. Similarly, Port A writes 0x3C to addr 7, then Port B overwrites addr 7 with 0x2B. So final values at addr 5 and 7 are 0x4D and 0x2B respectively. Only these two addresses changed, so 2 unique values stored.