Dual-port RAM design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Dual-Port RAM Write and Read

What is the output of the following Verilog testbench snippet that writes and reads from a dual-port RAM?

Verilog

module dual_port_ram(
  input wire clk,
  input wire we_a, we_b,
  input wire [3:0] addr_a, addr_b,
  input wire [7:0] din_a, din_b,
  output reg [7:0] dout_a, dout_b
);
  reg [7:0] ram [0:15];

  always @(posedge clk) begin
    if (we_a) ram[addr_a] <= din_a;
    dout_a <= ram[addr_a];
  end

  always @(posedge clk) begin
    if (we_b) ram[addr_b] <= din_b;
    dout_b <= ram[addr_b];
  end
endmodule

module testbench;
  reg clk = 0;
  reg we_a, we_b;
  reg [3:0] addr_a, addr_b;
  reg [7:0] din_a, din_b;
  wire [7:0] dout_a, dout_b;

  dual_port_ram ram_inst(clk, we_a, we_b, addr_a, addr_b, din_a, din_b, dout_a, dout_b);

  always #5 clk = ~clk;

  initial begin
    we_a = 1; addr_a = 4'd3; din_a = 8'hAA;
    we_b = 1; addr_b = 4'd3; din_b = 8'h55;
    #10;
    we_a = 0; we_b = 0;
    #10;
    $display("dout_a = %h, dout_b = %h", dout_a, dout_b);
    $finish;
  end
endmodule

A dout_a = 55, dout_b = 55

B dout_a = AA, dout_b = AA

C dout_a = AA, dout_b = 55

D dout_a = 55, dout_b = AA

💡 Hint

Remember that both ports write to the same address on the same clock edge. The order of writes affects the final stored value.

Both ports write to address 3 on the same clock edge. Port B's write happens after Port A's in the code, so the final stored value is 0x55. Both dout_a and dout_b read the updated value 0x55 after the clock edge.

🧠 Conceptual

intermediate

Understanding Dual-Port RAM Read Behavior

In a synchronous dual-port RAM, if both ports read from the same address simultaneously without any write enable active, what will be the output on both ports?

A Both ports output zero regardless of stored data.

B Both ports output the data from the other port's address.

C Both ports output the stored data at that address.

D One port outputs data, the other outputs undefined value.

💡 Hint

Think about how synchronous RAM reads work when no writes occur.

When no write occurs, both ports read the stored data at the requested address. Since both read the same address, both outputs show the stored value.

🔧 Debug

advanced

Identify the Bug in Dual-Port RAM Write Logic

What is the main problem in this dual-port RAM write logic snippet? always @(posedge clk) begin if (we_a) ram[addr_a] <= din_a; else if (we_b) ram[addr_b] <= din_b; end

A The clock edge sensitivity is incorrect.

B Both ports write simultaneously causing data corruption.

C The RAM array is not declared properly.

D Port B's write will never happen if Port A's write enable is true.

💡 Hint

Check how the if-else structure affects port B's write enable.

The else if means port B's write only happens if port A's write enable is false. But if port A's write enable is true, port B's write is skipped. This structure prevents simultaneous writes and may block port B's write incorrectly.

📝 Syntax

advanced

Syntax Error in Dual-Port RAM Declaration

Which option contains the correct syntax to declare a 16x8-bit dual-port RAM array in Verilog?

A reg ram [7:0] [0:15];

B reg [7:0] ram [0:15];

C reg [0:15] ram [7:0];

D reg [7:0] ram [15:0];

💡 Hint

Remember the order: data width first, then address range.

The correct syntax is reg [7:0] ram [0:15]; which means 16 locations (0 to 15) each 8 bits wide. Other options have incorrect dimension order or ranges.

🚀 Application

expert

Number of Unique Data Values Stored After Writes

Given a dual-port RAM with 16 addresses, initially all zero, the following writes occur simultaneously on the same clock edge: - Port A writes 8'h1A to address 5 - Port B writes 8'h2B to address 7 - Port A writes 8'h3C to address 7 - Port B writes 8'h4D to address 5 Assuming the write order in code is Port A then Port B for each port's write, how many unique data values are stored in the RAM after this clock edge?

A 2

B 4

C 1

D 3

💡 Hint

Consider that writes to the same address overwrite each other in order.

Port A writes 0x1A to addr 5, then Port B overwrites addr 5 with 0x4D. Similarly, Port A writes 0x3C to addr 7, then Port B overwrites addr 7 with 0x2B. So final values at addr 5 and 7 are 0x4D and 0x2B respectively. Only these two addresses changed, so 2 unique values stored.

Practice

1. What is the main advantage of using a dual-port RAM in hardware design?

easy

A. It allows two independent read/write operations simultaneously.

B. It reduces the size of the memory.

C. It makes the RAM slower but cheaper.

D. It only supports read operations.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM has two ports that can access memory independently at the same time.

2. Step 2: Identify the main benefit

   This allows simultaneous read/write operations, improving performance.

3. Final Answer:

   It allows two independent read/write operations simultaneously. -> Option A

4. Quick Check:

   Dual-port RAM = two simultaneous accesses [OK]

Hint: Dual-port RAM means two ports can access memory at once [OK]

Common Mistakes:

• Thinking it reduces memory size
• Assuming it only supports reads
• Believing it slows down RAM

2. Which of the following is the correct Verilog port declaration for a dual-port RAM with separate read and write ports?

easy

A. input clk, input [7:0] addr_a, output [7:0] data_out_a, input [7:0] addr_b, output [7:0] data_out_b;

B. input clk, input [7:0] addr, input [7:0] data_in, output [7:0] data_out, input we;

C. input clk, input [7:0] addr, output [7:0] data_out, input we, input re;

D. input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b;

Solution

1. Step 1: Identify dual-port RAM ports

   Dual-port RAM needs separate address, data, and write enable signals for each port.

2. Step 2: Match correct declaration

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; declares separate addr, data_in, data_out, and we signals for ports A and B, matching dual-port RAM design.

3. Final Answer:

   input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; -> Option D

4. Quick Check:

   Separate signals per port = input clk, input [7:0] addr_a, input [7:0] data_in_a, output [7:0] data_out_a, input we_a, input [7:0] addr_b, input [7:0] data_in_b, output [7:0] data_out_b, input we_b; [OK]

Hint: Dual-port RAM needs separate signals for each port [OK]

Common Mistakes:

• Using single address and data signals for both ports
• Missing write enable signals
• Confusing read and write signals

3. Given the following Verilog snippet for a dual-port RAM, what will be the value of data_out_b after the clock edge if we_b is 0 and addr_b is 3?

reg [7:0] ram [0:7];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

medium

A. The value of data_in_b.

B. The value stored at address 3 before the clock edge.

C. Zero, because we_b is 0.

D. Undefined, because data_out_b is not assigned.

Solution

1. Step 1: Understand write enable effect

   Since we_b is 0, no write occurs at addr_b on this clock edge.

2. Step 2: Determine data_out_b value

   data_out_b reads the RAM at addr_b, so it outputs the stored value at address 3 before the clock edge.

3. Final Answer:

   The value stored at address 3 before the clock edge. -> Option B

4. Quick Check:

   we_b=0 means no write; output = stored value [OK]

Hint: If write enable is 0, output shows stored memory value [OK]

Common Mistakes:

• Assuming data_out_b equals data_in_b always
• Thinking output is zero when no write
• Ignoring read operation on clock edge

4. Identify the error in this dual-port RAM Verilog code snippet:

reg [7:0] ram [0:15];
always @(posedge clk) begin
  if (we_a) ram[addr_a] <= data_in_a;
  if (we_b) ram[addr_b] <= data_in_b;
  data_out_a <= ram[addr_a];
  data_out_b <= ram[addr_b];
end

assign data_out_a = ram[addr_a];

medium

A. Conflicting assignments to data_out_a: both procedural and continuous.

B. Missing clock signal in sensitivity list.

C. Incorrect RAM size declaration.

D. No write enable signals declared.

Solution

1. Step 1: Check assignments to data_out_a

   Data_out_a is assigned inside the always block and also by continuous assign statement, causing conflict.

2. Step 2: Understand Verilog rules

   A signal cannot be driven by both procedural and continuous assignments simultaneously.

3. Final Answer:

   Conflicting assignments to data_out_a: both procedural and continuous. -> Option A

4. Quick Check:

   Signal driven twice = conflict error [OK]

Hint: Avoid assigning same signal in always block and assign statement [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking sensitivity list needs clock and addr
• Misunderstanding RAM size syntax

5. You want to design a dual-port RAM where Port A is write-only and Port B is read-only. Which modification correctly implements this behavior in Verilog?

hard

A. Disable clock on Port B to make it read-only.

B. Use write enable on both ports and read data from both ports.

C. Use write enable only on Port A and never write on Port B; read data only from Port B.

D. Use a single write enable for both ports.

Solution

1. Step 1: Define port roles

   Port A should only write data, so it needs a write enable and no read output.

2. Step 2: Configure Port B as read-only

   Port B should not write, so write enable is never asserted; it only reads data from RAM.

3. Final Answer:

   Use write enable only on Port A and never write on Port B; read data only from Port B. -> Option C

4. Quick Check:

   Write-only Port A + Read-only Port B = Use write enable only on Port A and never write on Port B; read data only from Port B. [OK]

Hint: Assign write enable only to write port, read from the other [OK]

Common Mistakes:

• Trying to write on both ports
• Disabling clock to control read/write
• Using single write enable for both ports