Down counter design in Verilog - Step-by-Step Execution

Concept Flow - Down counter design

Start with initial count

↓

Check if count > 0?

No→Stop or reset

Yes↓

Decrease count by 1

↓

Output current count

↓

Wait for next clock pulse

↩Back to Check

The down counter starts from an initial value, checks if it is greater than zero, decreases it by one each clock cycle, outputs the count, and repeats until zero.

Execution Sample

Verilog

module down_counter(
  input clk,
  input reset,
  output reg [3:0] count
);
  always @(posedge clk or posedge reset) begin
    if (reset) count <= 4'd10;
    else if (count > 0) count <= count - 1;
  end
endmodule

This Verilog module counts down from 10 to 0 on each clock pulse, resetting to 10 when reset is high.

Execution Table

Step	clk edge	reset	count before	Condition (count > 0)	Action	count after	Output
1	rising	1	X (undefined)	N/A	Reset active, count set to 10	10	10
2	rising	0	10	True	count = 10 - 1	9	9
3	rising	0	9	True	count = 9 - 1	8	8
4	rising	0	8	True	count = 8 - 1	7	7
5	rising	0	7	True	count = 7 - 1	6	6
6	rising	0	6	True	count = 6 - 1	5	5
7	rising	0	5	True	count = 5 - 1	4	4
8	rising	0	4	True	count = 4 - 1	3	3
9	rising	0	3	True	count = 3 - 1	2	2
10	rising	0	2	True	count = 2 - 1	1	1
11	rising	0	1	True	count = 1 - 1	0	0
12	rising	0	0	False	No decrement	0	0

💡 Count reaches 0, condition count > 0 is False, counting stops.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
count	X (undefined)	10	9	8	7	6	5	4	3	2	1	0	0

Key Moments - 3 Insights

Why does the count not go below zero?

Because the condition 'count > 0' is checked before decrementing (see execution_table step 12), so when count is 0, it stops decrementing.

What happens when reset is active?

At step 1 in the execution_table, reset sets count to 10 immediately regardless of previous value.

Why is the output the same as count after each step?

Because the output is directly the current count value after decrement or reset, shown in the 'Output' column matching 'count after'.

Visual Quiz - 3 Questions

Look at the execution_table at step 5, what is the count after decrement?

A 5

B 7

C 6

D 8

💡 Hint

Check the 'count after' column at step 5 in the execution_table.

At which step does the condition 'count > 0' become false?

A Step 12

B Step 10

C Step 11

D Step 1

💡 Hint

Look at the 'Condition (count > 0)' column in the execution_table.

If reset is activated again at step 6, what would be the count after that step?

A 5

B 10

C 6

D 0

💡 Hint

Reset sets count to 10 immediately as shown in step 1 of the execution_table.

Concept Snapshot

Down counter in Verilog:
- Use always block triggered by clock and reset
- On reset, set count to initial value
- On clock, if count > 0, decrement count
- Output current count
- Stops at zero, no negative values

Full Transcript

This visual execution traces a Verilog down counter module. It starts with an undefined count, then reset sets it to 10. On each rising clock edge, if count is greater than zero, it decreases by one. The output shows the current count after each decrement. When count reaches zero, the condition to decrement fails, so the count stays at zero. Reset can be triggered anytime to restart the count at 10. The variable tracker shows count values step by step. Key moments clarify why count never goes below zero and how reset works. The quiz tests understanding of count values at specific steps and reset behavior.

Practice

1.

What is the main function of a down counter in Verilog?

easy

A. Counts backward from a start value to zero

B. Counts forward from zero to a maximum value

C. Generates a clock signal

D. Resets the system to initial state

Solution

1. Step 1: Understand the counting direction

   A down counter decreases its count value each clock cycle, moving backward.

2. Step 2: Compare with other options

   Counting forward is for up counters, clock generation and reset are different functions.

3. Final Answer:

   Counts backward from a start value to zero -> Option A

4. Quick Check:

   Down counter = counts backward [OK]

Hint: Down counter always counts backward from start [OK]

Common Mistakes:

• Confusing down counter with up counter
• Thinking it generates clock signals
• Assuming it resets the system

2.

Which of the following is the correct Verilog syntax to declare a 4-bit down counter register?

?

easy

A. integer counter;

B. reg [3:0] counter;

C. reg counter[3:0];

D. wire [4:0] counter;

Solution

1. Step 1: Identify correct register declaration

   In Verilog, a 4-bit register is declared as reg [3:0] name; where 3:0 means 4 bits.

2. Step 2: Check other options

   wire is for connections, reg counter[3:0] is an array of 4 registers, integer is 32-bit signed.

3. Final Answer:

   reg [3:0] counter; -> Option B

4. Quick Check:

   4-bit reg = reg [3:0] name [OK]

Hint: Use reg [3:0] for 4-bit counters [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Declaring array instead of vector
• Using integer for fixed bit width

3.

Given this Verilog code snippet for a 3-bit down counter starting at 5, what is the value of count after 3 clock cycles?

reg [2:0] count = 3'd5;
always @(posedge clk) begin
  if (count > 0)
    count <= count - 1;
end

medium

A. 3

B. 5

C. 0

D. 2

Solution

1. Step 1: Trace the count value each clock

   Start at 5, after 1st clock: 4, 2nd clock: 3, 3rd clock: 2.

2. Step 2: Confirm counting stops only at zero

   Since count > 0 condition is true, it decrements each cycle until zero.

3. Final Answer:

   2 -> Option D

4. Quick Check:

   5 - 3 = 2 after 3 clocks [OK]

Hint: Subtract 1 each clock if count > 0 [OK]

Common Mistakes:

• Not decrementing count on each clock
• Stopping count too early
• Confusing initial value with current

4.

Identify the error in this down counter code and select the fix:

reg [3:0] count = 4'd10;
always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 4'd0;
  else if (count >= 0)
    count <= count - 1;
end

medium

A. Remove reset from sensitivity list

B. Initialize count to zero instead of 10

C. Change count >= 0 to count > 0

D. Use count <= count + 1 instead

Solution

1. Step 1: Analyze the condition for decrement

   Condition count >= 0 is always true for unsigned, causing underflow.

2. Step 2: Correct condition to prevent underflow

   Use count > 0 to stop decrement at zero and avoid wrap-around.

3. Final Answer:

   Change count >= 0 to count > 0 -> Option C

4. Quick Check:

   Prevent underflow by checking count > 0 [OK]

Hint: Use > 0, not >= 0, to stop at zero [OK]

Common Mistakes:

• Using >= 0 causes counter to wrap
• Ignoring reset sensitivity
• Incrementing instead of decrementing

5.

You want to design a 4-bit down counter that stops at zero and asserts an output done signal when zero is reached. Which Verilog code snippet correctly implements this behavior?

?

hard

A. reg [3:0] count = 4'd10;
reg done = 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4'd10;
done <= 0;
end else if (count > 0) begin
count <= count - 1;
done <= 0;
end else begin
done <= 1;
end
end

B. reg [3:0] count = 4'd10;
reg done = 0;
always @(posedge clk) begin
if (count >= 0) begin
count <= count - 1;
done <= (count == 0);
end
end

C. reg [3:0] count = 4'd0;
reg done = 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4'd10;
done <= 0;
end else begin
count <= count - 1;
done <= (count == 0);
end
end

D. reg [3:0] count = 4'd10;
reg done = 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4'd10;
done <= 0;
end else if (count >= 0) begin
count <= count - 1;
done <= 0;
end else begin
done <= 1;
end
end

Solution

1. Step 1: Check initialization and reset behavior

   Count starts at 10, done is 0, reset sets count and done correctly.

2. Step 2: Verify counting and done signal logic

   Count decrements only if > 0, done set to 1 when count reaches zero, stopping count.

3. Step 3: Compare with other options

   reg [3:0] count = 4'd10; reg done = 0; always @(posedge clk) begin if (count >= 0) begin count <= count - 1; done <= (count == 0); end end allows underflow. Other options either start count at 0 or use >= 0 causing wrap-around.

4. Final Answer:

   A -> Option A

5. Quick Check:

   Stop at zero and assert done = 1 [OK]

Hint: Stop count at zero, set done signal then [OK]

Common Mistakes:

• Allowing count to underflow below zero
• Incorrect done signal timing
• Wrong initial count value