Down counter design in Verilog - Step-by-Step Execution

Concept Flow - Down counter design

Start with initial count

↓

Check if count > 0?

No→Stop or reset

Yes↓

Decrease count by 1

↓

Output current count

↓

Wait for next clock pulse

↩Back to Check

The down counter starts from an initial value, checks if it is greater than zero, decreases it by one each clock cycle, outputs the count, and repeats until zero.

Execution Sample

Verilog

module down_counter(
  input clk,
  input reset,
  output reg [3:0] count
);
  always @(posedge clk or posedge reset) begin
    if (reset) count <= 4'd10;
    else if (count > 0) count <= count - 1;
  end
endmodule

This Verilog module counts down from 10 to 0 on each clock pulse, resetting to 10 when reset is high.

Execution Table

Step	clk edge	reset	count before	Condition (count > 0)	Action	count after	Output
1	rising	1	X (undefined)	N/A	Reset active, count set to 10	10	10
2	rising	0	10	True	count = 10 - 1	9	9
3	rising	0	9	True	count = 9 - 1	8	8
4	rising	0	8	True	count = 8 - 1	7	7
5	rising	0	7	True	count = 7 - 1	6	6
6	rising	0	6	True	count = 6 - 1	5	5
7	rising	0	5	True	count = 5 - 1	4	4
8	rising	0	4	True	count = 4 - 1	3	3
9	rising	0	3	True	count = 3 - 1	2	2
10	rising	0	2	True	count = 2 - 1	1	1
11	rising	0	1	True	count = 1 - 1	0	0
12	rising	0	0	False	No decrement	0	0

💡 Count reaches 0, condition count > 0 is False, counting stops.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
count	X (undefined)	10	9	8	7	6	5	4	3	2	1	0	0

Key Moments - 3 Insights

Why does the count not go below zero?

Because the condition 'count > 0' is checked before decrementing (see execution_table step 12), so when count is 0, it stops decrementing.

What happens when reset is active?

At step 1 in the execution_table, reset sets count to 10 immediately regardless of previous value.

Why is the output the same as count after each step?

Because the output is directly the current count value after decrement or reset, shown in the 'Output' column matching 'count after'.

Visual Quiz - 3 Questions

Look at the execution_table at step 5, what is the count after decrement?

A 5

B 7

C 6

D 8

💡 Hint

Check the 'count after' column at step 5 in the execution_table.

At which step does the condition 'count > 0' become false?

A Step 12

B Step 10

C Step 11

D Step 1

💡 Hint

Look at the 'Condition (count > 0)' column in the execution_table.

If reset is activated again at step 6, what would be the count after that step?

A 5

B 10

C 6

D 0

💡 Hint

Reset sets count to 10 immediately as shown in step 1 of the execution_table.

Concept Snapshot

Down counter in Verilog:
- Use always block triggered by clock and reset
- On reset, set count to initial value
- On clock, if count > 0, decrement count
- Output current count
- Stops at zero, no negative values

Full Transcript

This visual execution traces a Verilog down counter module. It starts with an undefined count, then reset sets it to 10. On each rising clock edge, if count is greater than zero, it decreases by one. The output shows the current count after each decrement. When count reaches zero, the condition to decrement fails, so the count stays at zero. Reset can be triggered anytime to restart the count at 10. The variable tracker shows count values step by step. Key moments clarify why count never goes below zero and how reset works. The quiz tests understanding of count values at specific steps and reset behavior.