Down counter design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit down counter

What is the output of the 4-bit down counter after 3 clock cycles if it starts at 4'b1010 (decimal 10)?

Verilog

module down_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 4'b1010;
    else
      count <= count - 1;
  end
endmodule

A 4'b1001

B 4'b0111

C 4'b0110

D 4'b0101

💡 Hint

Count down from 1010 three times, subtracting 1 each clock cycle.

Starting at 1010 (decimal 10), after 1 clock cycle: 1001 (9), after 2: 1000 (8), after 3: 0111 (7).

🧠 Conceptual

intermediate

Behavior of synchronous reset in down counter

In a synchronous reset down counter, what happens when the reset signal is asserted at the clock edge?

A The counter resets to initial value only at the next clock edge.

B The counter freezes and holds its current value indefinitely.

C The counter counts down twice in the same clock cycle.

D The counter resets to initial value immediately, ignoring the clock.

💡 Hint

Synchronous means reset works with the clock.

Synchronous reset means the reset action happens only on the clock edge, so the counter resets at the next clock edge after reset is asserted.

🔧 Debug

advanced

Identify the error in this down counter code

What error will this Verilog down counter code produce when simulated?

Verilog

module down_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset == 1'b1)
      count = 4'b1111;
    else
      count = count - 1;
  end
endmodule

A Synthesis warning: use non-blocking assignments (<=) inside always block.

B No error, code works correctly.

C Runtime error: count variable is not initialized.

D Syntax error: missing semicolon after count assignment.

💡 Hint

Check the type of assignment used inside sequential always block.

In sequential logic (inside always @(posedge clk)), non-blocking assignments (<=) should be used to avoid race conditions and ensure correct simulation and synthesis.

📝 Syntax

advanced

Syntax error in down counter module

Which option contains the correct syntax for a 3-bit down counter with asynchronous reset?

A

module down_counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk or posedge reset) begin
    if reset
      count <= 3'b000;
    else
      count <= count - 1;
  end
endmodule

B

module down_counter(input clk, input reset, output reg [2:0] count)
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 3'b000;
    else
      count <= count - 1;
  end
endmodule

C

module down_counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 3'b000;
    else
      count <= count - 1;
  end
endmodule

D

module down_counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset == 1'b1)
      count = 3'b000;
    else
      count = count - 1;
  end
endmodule

💡 Hint

Check for missing semicolons and correct if syntax.

Option C has correct module declaration, always block sensitivity list, if statement syntax, and uses non-blocking assignments.

🚀 Application

expert

Design a down counter with load and enable signals

Which Verilog code correctly implements a 4-bit down counter with synchronous load and enable signals? When load is high, the counter loads the input value; when enable is high and load is low, the counter counts down by 1 each clock cycle.

A

module down_counter(input clk, input reset, input load, input enable, input [3:0] data_in, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset)
      count <= 4'b0000;
    else if (load)
      count <= data_in;
    else if (enable)
      count <= count - 1;
  end
endmodule

B

module down_counter(input clk, input reset, input load, input enable, input [3:0] data_in, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 4'b0000;
    else if (enable)
      count <= count - 1;
    else if (load)
      count <= data_in;
  end
endmodule

C

module down_counter(input clk, input reset, input load, input enable, input [3:0] data_in, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset == 1'b1)
      count = 4'b0000;
    else if (load == 1'b1)
      count = data_in;
    else if (enable == 1'b1)
      count = count - 1;
  end
endmodule

D

module down_counter(input clk, input reset, input load, input enable, input [3:0] data_in, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 4'b0000;
    else if (load)
      count <= data_in;
    else if (enable)
      count <= count - 1;
  end
endmodule

💡 Hint

Reset should be asynchronous; load has priority over enable.

Option D correctly uses asynchronous reset, synchronous load with priority over enable, and non-blocking assignments. Option D misses asynchronous reset. Option D uses blocking assignments. Option D has wrong priority order (enable before load).