Down counter design in Verilog - Mini Project: Build & Apply

Down counter design

📖 Scenario: You are designing a simple digital down counter using Verilog. This counter will start from a specific number and count down to zero, decreasing by one each clock cycle.

🎯 Goal: Build a Verilog module for a down counter that counts down from 15 to 0 and then stops.

📋 What You'll Learn

Create a 4-bit register to hold the counter value

Initialize the counter to 15

Decrease the counter by 1 on each positive clock edge

Stop counting when the counter reaches 0

💡 Why This Matters

🌍 Real World

Down counters are used in digital clocks, timers, and event counters where counting down from a number is needed.

💼 Career

Understanding counters is fundamental for hardware design engineers working with digital circuits and FPGA programming.

1

Create the counter register and initialize it

Write a Verilog module named down_counter with inputs clk and reset. Inside, declare a 4-bit register called count and initialize it to 15 when reset is high.

Verilog

module down_counter(input clk, input reset);
    reg [3:0] count;
    // Your code here
endmodule

Need a hint?

Use an always block triggered on the positive edge of clk or reset. When reset is high, set count to 15.

2

Add the down counting logic

Inside the always block, add logic to decrease count by 1 on each positive clock edge when reset is low and count is greater than 0.

Verilog

module down_counter(input clk, input reset);
    reg [3:0] count;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            count <= 4'd15;
        end else begin
            // Your code here
        end
    end
endmodule

Need a hint?

Use an if statement to check if count is greater than zero before subtracting 1.

3

Add an output to show the current count

Add a 4-bit output port named count_out and assign it the value of the internal count register.

Verilog

module down_counter(input clk, input reset, output [3:0] count_out);
    reg [3:0] count;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            count  0) begin
                count <= count - 1;
            end
        end
    end
    // Your code here
endmodule

Need a hint?

Use an assign statement to connect the internal register count to the output count_out.

4

Test the down counter by printing the count

Write a simple testbench module named testbench that instantiates down_counter, applies a clock signal, asserts reset once, and prints the count_out value on each clock cycle for 20 cycles.

Verilog

module testbench;
    reg clk = 0;
    reg reset;
    wire [3:0] count_out;
    down_counter uut(clk, reset, count_out);

    // Your code here
endmodule

Need a hint?

Create a clock signal that toggles every 5 time units. Use initial block to assert reset at start, then release it. Use a repeat loop to print the count 20 times on clock rising edges.