Down counter design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit down counter register.

Verilog

reg [[1]:0] counter;

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A7

B4

C0

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4:0 which is 5 bits

Using 7:0 which is 8 bits

The counter is 4 bits wide, so the index goes from 3 down to 0.

2fill in blank

medium

Complete the code to decrement the counter by 1 on each clock cycle.

Verilog

always @(posedge clk) begin
  if (reset) counter <= 4'b1111;
  else counter <= counter [1] 1;
end

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A-

B+

C*

D/

Attempts:

3 left

💡 Hint

Common Mistakes

Using '+' which counts up

Using '*' or '/' which are not for decrementing

To count down, we subtract 1 from the counter each clock cycle.

3fill in blank

hard

Fix the error in the code to reset the counter to 15 when reset is active.

Verilog

always @(posedge clk) begin
  if (reset == [1]) counter <= 4'b1111;
  else counter <= counter - 1;
end

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A1

B0

Chigh

Dtrue

Attempts:

3 left

💡 Hint

Common Mistakes

Using 0 which means reset inactive

Using 'true' or 'high' which are not valid in Verilog

The reset signal is active high, so it should be compared to 1.

4fill in blank

hard

Fill both blanks to complete the code that wraps the counter to 15 when it reaches 0.

Verilog

always @(posedge clk) begin
  if (reset) counter <= 4'b1111;
  else if (counter == [1]) counter <= [2];
  else counter <= counter - 1;
end

Drag options to blanks, or click blank then click option'

A4'b0000

B4'b1111

C4'b0001

D4'b1110

Attempts:

3 left

💡 Hint

Common Mistakes

Using 1 instead of 0 for the check

Setting counter to 14 instead of 15

When the counter reaches 0 (4'b0000), it wraps back to 15 (4'b1111).

5fill in blank

hard

Fill all three blanks to complete the module declaration and port list for the down counter.

Verilog

module down_counter(
  input wire [1],
  input wire [2],
  output reg [3:0] [3]
);

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Aclk

Breset

Ccounter

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using enable instead of reset

Naming output as enable instead of counter

The module has inputs clk and reset, and a 4-bit output counter.