Default case importance in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to add a default case in the always block.

Verilog

always @(*) begin
  case (state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    [1]
  endcase
end

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Adefault: out = 1'b0;

Belse: out = 1'b0;

Cotherwise: out = 1'b0;

Dcase_default: out = 1'b0;

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'else' or 'otherwise' instead of 'default' in case statements.

The default keyword is used in Verilog case statements to specify what happens if no other case matches.

2fill in blank

medium

Complete the code to ensure the output is assigned in all cases.

Verilog

always @(*) begin
  case (opcode)
    3'b000: result = a + b;
    3'b001: result = a - b;
    [1]
  endcase
end

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Adefault: result = a;

Bdefault: result = 0;

Cdefault: result = b;

Ddefault: result = 1;

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting the default case causing inferred latches.

The default case ensures result is assigned a value even if opcode doesn't match known cases, preventing latches.

3fill in blank

hard

Fix the error in the case statement by completing the default case.

Verilog

always @(*) begin
  case (sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    [1]
  endcase
end

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Adefault: out = in3;

Bdefault: out = 1'bx;

Cdefault: out = 1'b0;

Ddefault: out = 1'b1;

Attempts:

3 left

💡 Hint

Common Mistakes

Using 1'bx which can cause simulation mismatches or synthesis issues.

Assigning 1'b0 in the default case prevents latches and sets a known safe output.

4fill in blank

hard

Complete the code to add a default case that prevents latches.

Verilog

always @(*) begin
  case (cmd)
    3'b000: action = 2'b01;
    3'b001: action = 2'b10;
    [1]
  endcase
end

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Adefault: action = 2'b00;

Bdefault: action = 2'b11;

Caction = 2'b00;

Daction = 2'b11;

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting the default case causing inferred latches.

The default case ensures action is assigned a safe value even for unknown cmd, preventing inferred latches.

5fill in blank

hard

Fill all three blanks to write a safe combinational block with a default case.

Verilog

always @(*) begin
  [1] = 0;
  case (state)
    2'b00: [2] = 1;
    2'b01: [3] = 0;
    default: [2] = 0;
  endcase
end

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Aout

Dtemp

Attempts:

3 left

💡 Hint

Common Mistakes

Using different variable names causing confusion or latches.

Assigning out before the case and in each case arm ensures no latches are inferred and output is always defined.