Default case importance in Verilog - Mini Project: Build & Apply

Default Case Importance in Verilog

📖 Scenario: You are designing a simple traffic light controller using Verilog. The controller uses a state variable to decide which light to turn on: red, yellow, or green.

🎯 Goal: Build a Verilog module that uses a case statement with a default case to handle unexpected states safely.

📋 What You'll Learn

Create a reg [1:0] state variable with initial value 2'b00

Create a reg [2:0] lights variable to represent red, yellow, and green lights

Use a case statement on state with cases for 2'b00, 2'b01, 2'b10

Include a default case that turns off all lights

Print the value of lights after the case statement

💡 Why This Matters

🌍 Real World

Traffic light controllers and many hardware designs use <code>case</code> statements with <code>default</code> to ensure safe behavior even if unexpected inputs occur.

💼 Career

Understanding how to use <code>default</code> cases in hardware description languages like Verilog is essential for designing reliable digital circuits and avoiding unintended hardware states.

1

Create the initial state and lights variables

Create a reg [1:0] state variable and set it to 2'b00. Also create a reg [2:0] lights variable initialized to 3'b000.

Verilog

// Your code here to declare and initialize state and lights

Hint

Use reg [1:0] state = 2'b00; and reg [2:0] lights = 3'b000; to declare and initialize.

2

Add a case statement for the traffic light states

Write a case statement on state with these cases: 2'b00 sets lights = 3'b100 (red), 2'b01 sets lights = 3'b010 (yellow), and 2'b10 sets lights = 3'b001 (green).

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

// Add a case statement on state to set lights

Hint

Use case(state) with each state setting lights accordingly.

3

Add a default case to handle unexpected states

Add a default case inside the case(state) statement that sets lights = 3'b000 to turn off all lights.

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

always @* begin
    case(state)
        2'b00: lights = 3'b100; // red
        2'b01: lights = 3'b010; // yellow
        2'b10: lights = 3'b001; // green
        // Add default case here
    endcase
end

Hint

The default case catches any unexpected state values.

4

Print the lights value after the case statement

Add a initial block that displays the value of lights using $display.

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

always @* begin
    case(state)
        2'b00: lights = 3'b100; // red
        2'b01: lights = 3'b010; // yellow
        2'b10: lights = 3'b001; // green
        default: lights = 3'b000; // all off
    endcase
end

// Add initial block to display lights

Hint

Use initial block and $display("Lights: %b", lights); to print.

Practice

1.

Why is the default case important in a Verilog case statement?

easy

A. It handles all unmatched inputs to avoid unintended behavior.

B. It speeds up the simulation time significantly.

C. It is required to declare all variables in the module.

D. It automatically optimizes the hardware for speed.

Solution

1. Step 1: Understand the role of default in case

   The default case catches any input values not explicitly matched by other cases.

2. Step 2: Recognize the impact on hardware behavior

   Without a default, unmatched inputs can cause unintended latches or unpredictable outputs.

3. Final Answer:

   It handles all unmatched inputs to avoid unintended behavior. -> Option A

4. Quick Check:

   Default case = safe unmatched input handling [OK]

Hint: Default handles unmatched inputs to prevent errors [OK]

Common Mistakes:

• Thinking default speeds up simulation
• Believing default declares variables
• Assuming default optimizes hardware automatically

2.

Which of the following is the correct syntax for including a default case in a Verilog case statement?

case (sel)
  2'b00: out = 1;
  2'b01: out = 0;
  // What is the correct default syntax?
endcase

easy

A. otherwise: out = 1'bx;

B. else: out = 1'bx;

C. default: out = 1'bx;

D. case default: out = 1'bx;

Solution

1. Step 1: Recall Verilog case syntax

   The default keyword is used to specify the default case in a case statement.

2. Step 2: Identify correct syntax

   The correct syntax is default: statement;. Other keywords like else or otherwise are invalid in Verilog case.

3. Final Answer:

   default: out = 1'bx; -> Option C

4. Quick Check:

   Default syntax = "default:" [OK]

Hint: Use 'default:' keyword exactly in case statements [OK]

Common Mistakes:

• Using 'else' or 'otherwise' instead of 'default'
• Writing 'case default:' which is invalid
• Omitting the colon after default

3.

What is the output of the following Verilog code snippet if sel = 2'b10?

reg out;
always @(*) begin
  case (sel)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'bx;
  endcase
end

medium

A. out = 1'bz

B. out = 1'b1

C. out = 1'b0

D. out = 1'bx

Solution

1. Step 1: Check the value of sel

   The input sel is 2'b10, which is not matched by any explicit case.

2. Step 2: Determine which case executes

   Since 2'b10 is unmatched, the default case runs, setting out = 1'bx.

3. Final Answer:

   out = 1'bx -> Option D

4. Quick Check:

   Unmatched input triggers default = 1'bx [OK]

Hint: Unmatched case triggers default output [OK]

Common Mistakes:

• Assuming output stays at previous value
• Confusing default with last matched case
• Expecting output to be 0 or 1 without default

4.

Identify the problem in this Verilog case statement and how to fix it:

always @(*) begin
  case (state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
  endcase
end

medium

A. Missing default case can cause unintended latch inference.

B. The case keyword is misspelled.

C. The out variable is not declared.

D. The always block should use @(posedge clk) instead.

Solution

1. Step 1: Analyze the case statement coverage

   The case only covers two states but does not handle other possible values of state.

2. Step 2: Understand hardware implications

   Without a default, the synthesizer may infer a latch to hold out when state is unmatched.

3. Final Answer:

   Missing default case can cause unintended latch inference. -> Option A

4. Quick Check:

   Missing default = latch risk [OK]

Hint: Always add default to avoid latches [OK]

Common Mistakes:

• Ignoring latch inference from incomplete cases
• Thinking missing default causes syntax error
• Assuming always @(*) needs clock edge

5.

You have a 3-bit input sel controlling an output out with a case statement. You want to ensure no latches are inferred and all inputs are safely handled. Which is the best way to write the case?

always @(*) begin
  case (sel)
    3'b000: out = 1'b0;
    3'b001: out = 1'b1;
    3'b010: out = 1'b0;
    3'b011: out = 1'b1;
    3'b100: out = 1'b0;
    3'b101: out = 1'b1;
    3'b110: out = 1'b0;
    // What about 3'b111?
  endcase
end

hard

A. Leave 3'b111 unhandled to save code size.

B. Add a default case to assign out a safe value for 3'b111.

C. Add an if statement outside the case for 3'b111.

D. Use a for loop to cover all cases instead.

Solution

1. Step 1: Identify missing case coverage

   The input 3'b111 is not covered explicitly in the case statement.

2. Step 2: Prevent latch inference and ensure safe output

   Adding a default case assigns out a known value for unmatched inputs, preventing latches and undefined behavior.

3. Final Answer:

   Add a default case to assign out a safe value for 3'b111. -> Option B

4. Quick Check:

   Default case covers all inputs safely [OK]

Hint: Use default to cover all missing inputs [OK]

Common Mistakes:

• Ignoring missing input cases
• Trying to handle missing cases outside the case statement
• Using loops which are invalid in this context