Default case importance in Verilog - Mini Project: Build & Apply

Default Case Importance in Verilog

📖 Scenario: You are designing a simple traffic light controller using Verilog. The controller uses a state variable to decide which light to turn on: red, yellow, or green.

🎯 Goal: Build a Verilog module that uses a case statement with a default case to handle unexpected states safely.

📋 What You'll Learn

Create a reg [1:0] state variable with initial value 2'b00

Create a reg [2:0] lights variable to represent red, yellow, and green lights

Use a case statement on state with cases for 2'b00, 2'b01, 2'b10

Include a default case that turns off all lights

Print the value of lights after the case statement

💡 Why This Matters

🌍 Real World

Traffic light controllers and many hardware designs use <code>case</code> statements with <code>default</code> to ensure safe behavior even if unexpected inputs occur.

💼 Career

Understanding how to use <code>default</code> cases in hardware description languages like Verilog is essential for designing reliable digital circuits and avoiding unintended hardware states.

1

Create the initial state and lights variables

Create a reg [1:0] state variable and set it to 2'b00. Also create a reg [2:0] lights variable initialized to 3'b000.

Verilog

// Your code here to declare and initialize state and lights

Need a hint?

Use reg [1:0] state = 2'b00; and reg [2:0] lights = 3'b000; to declare and initialize.

2

Add a case statement for the traffic light states

Write a case statement on state with these cases: 2'b00 sets lights = 3'b100 (red), 2'b01 sets lights = 3'b010 (yellow), and 2'b10 sets lights = 3'b001 (green).

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

// Add a case statement on state to set lights

Need a hint?

Use case(state) with each state setting lights accordingly.

3

Add a default case to handle unexpected states

Add a default case inside the case(state) statement that sets lights = 3'b000 to turn off all lights.

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

always @* begin
    case(state)
        2'b00: lights = 3'b100; // red
        2'b01: lights = 3'b010; // yellow
        2'b10: lights = 3'b001; // green
        // Add default case here
    endcase
end

Need a hint?

The default case catches any unexpected state values.

4

Print the lights value after the case statement

Add a initial block that displays the value of lights using $display.

Verilog

reg [1:0] state = 2'b00;
reg [2:0] lights = 3'b000;

always @* begin
    case(state)
        2'b00: lights = 3'b100; // red
        2'b01: lights = 3'b010; // yellow
        2'b10: lights = 3'b001; // green
        default: lights = 3'b000; // all off
    endcase
end

// Add initial block to display lights

Need a hint?

Use initial block and $display("Lights: %b", lights); to print.