Default case importance in Verilog - Time & Space Complexity

Time Complexity: Default case importance

O(1)

Understanding Time Complexity

When we write Verilog code with case statements, the default case helps cover all unexpected inputs.

We want to see how including or missing the default case affects how long the code takes to run.

Scenario Under Consideration

Analyze the time complexity of the following Verilog case statement.

always @(*) begin
  case (opcode)
    3'b000: out = a + b;
    3'b001: out = a - b;
    3'b010: out = a & b;
    3'b011: out = a | b;
    default: out = 0;
  endcase
end
    

This code chooses an operation based on opcode and uses a default to handle unexpected values.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The case statement checks the opcode once per evaluation.
• How many times: It runs once every time the inputs change, no loops inside.

How Execution Grows With Input

Since the case statement checks the opcode once per change, the number of operations stays the same no matter how many opcodes exist.

Input Size (number of opcodes)	Approx. Operations
10	1 check per input change
100	1 check per input change
1000	1 check per input change

Pattern observation: The execution time does not grow with more cases because the hardware checks the opcode in parallel.

Final Time Complexity

Time Complexity: O(1)

This means the time to decide the output stays the same no matter how many cases or if a default is present.

Common Mistake

[X] Wrong: "Adding a default case makes the code slower because it adds extra checks."

[OK] Correct: The default case is just a safety net and does not add extra time because hardware checks all cases at once.

Interview Connect

Understanding that default cases do not slow down your hardware logic shows you know how hardware works differently from software.

This helps you explain your design choices clearly and confidently.

Self-Check

"What if we removed the default case and the opcode had an unexpected value? How would that affect the behavior and timing?"