Default case importance in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog code without a default case?

Consider the following Verilog always block that uses a case statement without a default case. What will be the value of out when sel is 2'b11?

Verilog

reg [1:0] sel;
reg [3:0] out;
always @(*) begin
  case(sel)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
  endcase
end

A out retains its previous value (no change)

B Simulation error occurs

C out is set to 4'b0000

D out is set to 4'b1000

💡 Hint

Think about what happens when none of the case conditions match and there is no default.

Without a default case, if sel is 2'b11, none of the cases match, so out keeps its previous value. This can cause unintended latches in synthesis.

🧠 Conceptual

intermediate

Why is a default case important in combinational logic?

In Verilog, why should you always include a default case in a case statement for combinational logic?

A To prevent unintended latches by ensuring all outputs are assigned

B To make the code run faster in simulation

C To reduce the number of flip-flops used in the design

D To allow synthesis tools to ignore unused inputs

💡 Hint

Think about what happens if some outputs are not assigned in all cases.

Including a default ensures that outputs are assigned in every possible case, preventing unintended memory elements (latches) in combinational logic.

🔧 Debug

advanced

Identify the problem caused by missing default in this code

Given this Verilog snippet, what problem can arise during synthesis?

Verilog

reg [2:0] sel;
reg [7:0] data_out;
always @(*) begin
  case(sel)
    3'b000: data_out = 8'hAA;
    3'b001: data_out = 8'hBB;
    3'b010: data_out = 8'hCC;
    3'b011: data_out = 8'hDD;
    3'b100: data_out = 8'hEE;
  endcase
end

A data_out will always be zero regardless of sel

B Synthesis tool will optimize data_out to a constant value

C Compilation will fail with syntax error

D Unintended latch inferred because data_out is not assigned for all sel values

💡 Hint

Check if data_out is assigned for all possible sel values.

Since sel can be 3 bits (0 to 7), but only 5 cases are covered without a default, synthesis infers a latch to hold data_out when sel is outside those cases.

📝 Syntax

advanced

Which option correctly adds a default case to avoid latches?

Choose the correct way to add a default case to this case statement to avoid unintended latches.

Verilog

reg [1:0] sel;
reg [3:0] out;
always @(*) begin
  case(sel)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
  endcase
end

A Add: else: out = 4'b0000; inside the case statement

B Add: default out = 4'b0000; inside the case statement

C Add: default: out = 4'b0000; inside the case statement

D Add: default: out == 4'b0000; inside the case statement

💡 Hint

Remember the correct syntax for a default case in Verilog case statements.

The correct syntax is default: out = 4'b0000;. Options B, C, and D have syntax errors.

🚀 Application

expert

How many latches are inferred by this code and why?

Analyze this Verilog code. How many latches will synthesis infer and why?

Verilog

reg [1:0] sel;
reg [3:0] out1, out2;
always @(*) begin
  case(sel)
    2'b00: begin
      out1 = 4'b0001;
      out2 = 4'b1111;
    end
    2'b01: begin
      out1 = 4'b0010;
      // out2 not assigned here
    end
    2'b10: begin
      // out1 not assigned here
      out2 = 4'b0101;
    end
    default: begin
      out1 = 4'b0000;
      out2 = 4'b0000;
    end
  endcase
end

A One latch for out2 only

B Two latches: one for out1 and one for out2 due to missing assignments in some cases

C One latch for out1 only

D No latches because default assigns both outputs

💡 Hint

Check if all outputs are assigned in every case including default.

Even though default assigns both outputs, in cases 2'b01 and 2'b10, one of the outputs is not assigned, causing latches for both out1 and out2.

Practice

1.

Why is the default case important in a Verilog case statement?

easy

A. It handles all unmatched inputs to avoid unintended behavior.

B. It speeds up the simulation time significantly.

C. It is required to declare all variables in the module.

D. It automatically optimizes the hardware for speed.

Solution

1. Step 1: Understand the role of default in case

   The default case catches any input values not explicitly matched by other cases.

2. Step 2: Recognize the impact on hardware behavior

   Without a default, unmatched inputs can cause unintended latches or unpredictable outputs.

3. Final Answer:

   It handles all unmatched inputs to avoid unintended behavior. -> Option A

4. Quick Check:

   Default case = safe unmatched input handling [OK]

Hint: Default handles unmatched inputs to prevent errors [OK]

Common Mistakes:

• Thinking default speeds up simulation
• Believing default declares variables
• Assuming default optimizes hardware automatically

2.

Which of the following is the correct syntax for including a default case in a Verilog case statement?

case (sel)
  2'b00: out = 1;
  2'b01: out = 0;
  // What is the correct default syntax?
endcase

easy

A. otherwise: out = 1'bx;

B. else: out = 1'bx;

C. default: out = 1'bx;

D. case default: out = 1'bx;

Solution

1. Step 1: Recall Verilog case syntax

   The default keyword is used to specify the default case in a case statement.

2. Step 2: Identify correct syntax

   The correct syntax is default: statement;. Other keywords like else or otherwise are invalid in Verilog case.

3. Final Answer:

   default: out = 1'bx; -> Option C

4. Quick Check:

   Default syntax = "default:" [OK]

Hint: Use 'default:' keyword exactly in case statements [OK]

Common Mistakes:

• Using 'else' or 'otherwise' instead of 'default'
• Writing 'case default:' which is invalid
• Omitting the colon after default

3.

What is the output of the following Verilog code snippet if sel = 2'b10?

reg out;
always @(*) begin
  case (sel)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'bx;
  endcase
end

medium

A. out = 1'bz

B. out = 1'b1

C. out = 1'b0

D. out = 1'bx

Solution

1. Step 1: Check the value of sel

   The input sel is 2'b10, which is not matched by any explicit case.

2. Step 2: Determine which case executes

   Since 2'b10 is unmatched, the default case runs, setting out = 1'bx.

3. Final Answer:

   out = 1'bx -> Option D

4. Quick Check:

   Unmatched input triggers default = 1'bx [OK]

Hint: Unmatched case triggers default output [OK]

Common Mistakes:

• Assuming output stays at previous value
• Confusing default with last matched case
• Expecting output to be 0 or 1 without default

4.

Identify the problem in this Verilog case statement and how to fix it:

always @(*) begin
  case (state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
  endcase
end

medium

A. Missing default case can cause unintended latch inference.

B. The case keyword is misspelled.

C. The out variable is not declared.

D. The always block should use @(posedge clk) instead.

Solution

1. Step 1: Analyze the case statement coverage

   The case only covers two states but does not handle other possible values of state.

2. Step 2: Understand hardware implications

   Without a default, the synthesizer may infer a latch to hold out when state is unmatched.

3. Final Answer:

   Missing default case can cause unintended latch inference. -> Option A

4. Quick Check:

   Missing default = latch risk [OK]

Hint: Always add default to avoid latches [OK]

Common Mistakes:

• Ignoring latch inference from incomplete cases
• Thinking missing default causes syntax error
• Assuming always @(*) needs clock edge

5.

You have a 3-bit input sel controlling an output out with a case statement. You want to ensure no latches are inferred and all inputs are safely handled. Which is the best way to write the case?

always @(*) begin
  case (sel)
    3'b000: out = 1'b0;
    3'b001: out = 1'b1;
    3'b010: out = 1'b0;
    3'b011: out = 1'b1;
    3'b100: out = 1'b0;
    3'b101: out = 1'b1;
    3'b110: out = 1'b0;
    // What about 3'b111?
  endcase
end

hard

A. Leave 3'b111 unhandled to save code size.

B. Add a default case to assign out a safe value for 3'b111.

C. Add an if statement outside the case for 3'b111.

D. Use a for loop to cover all cases instead.

Solution

1. Step 1: Identify missing case coverage

   The input 3'b111 is not covered explicitly in the case statement.

2. Step 2: Prevent latch inference and ensure safe output

   Adding a default case assigns out a known value for unmatched inputs, preventing latches and undefined behavior.

3. Final Answer:

   Add a default case to assign out a safe value for 3'b111. -> Option B

4. Quick Check:

   Default case covers all inputs safely [OK]

Hint: Use default to cover all missing inputs [OK]

Common Mistakes:

• Ignoring missing input cases
• Trying to handle missing cases outside the case statement
• Using loops which are invalid in this context