Default case importance in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog code without a default case?

Consider the following Verilog always block that uses a case statement without a default case. What will be the value of out when sel is 2'b11?

Verilog

reg [1:0] sel;
reg [3:0] out;
always @(*) begin
  case(sel)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
  endcase
end

A out retains its previous value (no change)

B Simulation error occurs

C out is set to 4'b0000

D out is set to 4'b1000

💡 Hint

Think about what happens when none of the case conditions match and there is no default.

Without a default case, if sel is 2'b11, none of the cases match, so out keeps its previous value. This can cause unintended latches in synthesis.

🧠 Conceptual

intermediate

Why is a default case important in combinational logic?

In Verilog, why should you always include a default case in a case statement for combinational logic?

A To prevent unintended latches by ensuring all outputs are assigned

B To make the code run faster in simulation

C To reduce the number of flip-flops used in the design

D To allow synthesis tools to ignore unused inputs

💡 Hint

Think about what happens if some outputs are not assigned in all cases.

Including a default ensures that outputs are assigned in every possible case, preventing unintended memory elements (latches) in combinational logic.

🔧 Debug

advanced

Identify the problem caused by missing default in this code

Given this Verilog snippet, what problem can arise during synthesis?

Verilog

reg [2:0] sel;
reg [7:0] data_out;
always @(*) begin
  case(sel)
    3'b000: data_out = 8'hAA;
    3'b001: data_out = 8'hBB;
    3'b010: data_out = 8'hCC;
    3'b011: data_out = 8'hDD;
    3'b100: data_out = 8'hEE;
  endcase
end

A data_out will always be zero regardless of sel

B Synthesis tool will optimize data_out to a constant value

C Compilation will fail with syntax error

D Unintended latch inferred because data_out is not assigned for all sel values

💡 Hint

Check if data_out is assigned for all possible sel values.

Since sel can be 3 bits (0 to 7), but only 5 cases are covered without a default, synthesis infers a latch to hold data_out when sel is outside those cases.

📝 Syntax

advanced

Which option correctly adds a default case to avoid latches?

Choose the correct way to add a default case to this case statement to avoid unintended latches.

Verilog

reg [1:0] sel;
reg [3:0] out;
always @(*) begin
  case(sel)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
  endcase
end

A Add: else: out = 4'b0000; inside the case statement

B Add: default out = 4'b0000; inside the case statement

C Add: default: out = 4'b0000; inside the case statement

D Add: default: out == 4'b0000; inside the case statement

💡 Hint

Remember the correct syntax for a default case in Verilog case statements.

The correct syntax is default: out = 4'b0000;. Options B, C, and D have syntax errors.

🚀 Application

expert

How many latches are inferred by this code and why?

Analyze this Verilog code. How many latches will synthesis infer and why?

Verilog

reg [1:0] sel;
reg [3:0] out1, out2;
always @(*) begin
  case(sel)
    2'b00: begin
      out1 = 4'b0001;
      out2 = 4'b1111;
    end
    2'b01: begin
      out1 = 4'b0010;
      // out2 not assigned here
    end
    2'b10: begin
      // out1 not assigned here
      out2 = 4'b0101;
    end
    default: begin
      out1 = 4'b0000;
      out2 = 4'b0000;
    end
  endcase
end

A One latch for out2 only

B Two latches: one for out1 and one for out2 due to missing assignments in some cases

C One latch for out1 only

D No latches because default assigns both outputs

💡 Hint

Check if all outputs are assigned in every case including default.

Even though default assigns both outputs, in cases 2'b01 and 2'b10, one of the outputs is not assigned, causing latches for both out1 and out2.