0
0
Verilogprogramming~10 mins

State encoding (binary, one-hot, gray) in Verilog - Interactive Code Practice

Choose your learning style9 modes available
Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to declare a 2-bit binary state register.

Verilog
reg [[1]:0] state;
Drag options to blanks, or click blank then click option'
A1
B2
C3
D0
Attempts:
3 left
💡 Hint
Common Mistakes
Using 2 instead of 1 as the most significant bit index.
Forgetting that bit indexing starts at 0.
2fill in blank
medium

Complete the code to assign a one-hot encoded state for state 2.

Verilog
assign one_hot_state = 4'b[1];
Drag options to blanks, or click blank then click option'
A0010
B0001
C1000
D0100
Attempts:
3 left
💡 Hint
Common Mistakes
Setting the wrong bit high for the given state.
Confusing binary index order.
3fill in blank
hard

Fix the error in the Gray code assignment for 3-bit states.

Verilog
assign gray_state = state ^ (state >> [1]);
Drag options to blanks, or click blank then click option'
A3
B2
C1
D0
Attempts:
3 left
💡 Hint
Common Mistakes
Using shift amounts other than 1.
Forgetting to use XOR operator.
4fill in blank
hard

Fill both blanks to complete the binary to one-hot conversion.

Verilog
assign one_hot = 1 << [1]; // shift 1 by state index [2]
Drag options to blanks, or click blank then click option'
Astate
B1
Cstate + 1
D0
Attempts:
3 left
💡 Hint
Common Mistakes
Using a fixed number instead of the state variable for shifting.
Incorrect comment that does not match the code.
5fill in blank
hard

Fill all three blanks to complete the Gray code to binary conversion.

Verilog
always @(*) begin
  binary[WIDTH-1] = [1];
  for (int i = WIDTH-2; i >= [2]; i = i - 1) begin
    binary[i] = binary[i+1] ^ [3][i];
  end
end
Drag options to blanks, or click blank then click option'
Agray[WIDTH-1]
B0
Cgray
Dbinary
Attempts:
3 left
💡 Hint
Common Mistakes
Initializing binary incorrectly.
Using wrong indices in the loop.
Mixing up Gray and binary variables.