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Verilogprogramming~20 mins

State encoding (binary, one-hot, gray) in Verilog - Practice Problems & Coding Challenges

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Challenge - 5 Problems
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❓ Predict Output
intermediate
2:00remaining
Output of binary encoded state machine

What is the output of the following Verilog code snippet that uses binary state encoding?

Verilog
module fsm_binary(input clk, input rst, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (00). After 3 clock cycles, what is the state value?
A2'b10
B2'b01
C2'b00
D2'b11
Attempts:
2 left
💡 Hint

Trace the state transitions starting from S0 for 3 clock cycles.

❓ Predict Output
intermediate
2:00remaining
One-hot encoding state output

Given this one-hot encoded FSM, what is the value of state after 2 clock cycles?

Verilog
module fsm_onehot(input clk, input rst, output reg [2:0] state);
  parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (001). After 2 clock cycles, what is the state value?
A3'b100
B3'b010
C3'b001
D3'b111
Attempts:
2 left
💡 Hint

Follow the one-hot transitions from S0 through S1 to S2.

❓ Predict Output
advanced
2:00remaining
Gray code state transitions output

What is the output state after 4 clock cycles in this Gray code encoded FSM?

Verilog
module fsm_gray(input clk, input rst, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S3;
      S3: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (00). After 4 clock cycles, what is the state value?
A2'b01
B2'b10
C2'b11
D2'b00
Attempts:
2 left
💡 Hint

Trace the Gray code sequence through all states for 4 cycles.

🔧 Debug
advanced
2:00remaining
Identify error in one-hot FSM code

Which option contains the error that will cause a synthesis or runtime problem in this one-hot FSM code?

Verilog
module fsm_onehot_bug(input clk, input rst, output reg [2:0] state);
  parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= 3'b110; // suspicious
      default: state <= S0;
    endcase
  end
endmodule
AParameter values are not declared as localparam
BAssigning 3'b110 to state in S2 case breaks one-hot encoding
CUsing blocking assignment (=) instead of non-blocking (<=) in always block
DMissing default case in the case statement
Attempts:
2 left
💡 Hint

Check if the assigned state values maintain one-hot encoding.

🧠 Conceptual
expert
2:00remaining
Minimal bit width for Gray code FSM

You have a FSM with 10 states encoded using Gray code. What is the minimal number of bits required to encode all states uniquely?

A4 bits
B5 bits
C3 bits
D6 bits
Attempts:
2 left
💡 Hint

Think about how many unique states can be represented by n bits.