State encoding (binary, one-hot, gray) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of binary encoded state machine

What is the output of the following Verilog code snippet that uses binary state encoding?

Verilog

module fsm_binary(input clk, input rst, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (00). After 3 clock cycles, what is the state value?

A 2'b10

B 2'b01

C 2'b00

D 2'b11

💡 Hint

Trace the state transitions starting from S0 for 3 clock cycles.

The state machine cycles through S0 (00), S1 (01), S2 (10), then back to S0 (00). After 3 cycles, it returns to S0 (00).

❓ Predict Output

intermediate

One-hot encoding state output

Given this one-hot encoded FSM, what is the value of state after 2 clock cycles?

Verilog

module fsm_onehot(input clk, input rst, output reg [2:0] state);
  parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (001). After 2 clock cycles, what is the state value?

A 3'b100

B 3'b010

C 3'b001

D 3'b111

💡 Hint

Follow the one-hot transitions from S0 through S1 to S2.

The FSM moves from S0 (001) to S1 (010) after 1 clock, then to S2 (100) after 2 clocks.

❓ Predict Output

advanced

Gray code state transitions output

What is the output state after 4 clock cycles in this Gray code encoded FSM?

Verilog

module fsm_gray(input clk, input rst, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= S3;
      S3: state <= S0;
      default: state <= S0;
    endcase
  end
endmodule

// Initial state is S0 (00). After 4 clock cycles, what is the state value?

A 2'b01

B 2'b10

C 2'b11

D 2'b00

💡 Hint

Trace the Gray code sequence through all states for 4 cycles.

The FSM cycles through S0 (00), S1 (01), S2 (11), S3 (10), then back to S0 (00). After 4 cycles, it returns to S0.

🔧 Debug

advanced

Identify error in one-hot FSM code

Which option contains the error that will cause a synthesis or runtime problem in this one-hot FSM code?

Verilog

module fsm_onehot_bug(input clk, input rst, output reg [2:0] state);
  parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
  always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else case(state)
      S0: state <= S1;
      S1: state <= S2;
      S2: state <= 3'b110; // suspicious
      default: state <= S0;
    endcase
  end
endmodule

A Parameter values are not declared as localparam

B Assigning 3'b110 to state in S2 case breaks one-hot encoding

C Using blocking assignment (=) instead of non-blocking (<=) in always block

D Missing default case in the case statement

💡 Hint

Check if the assigned state values maintain one-hot encoding.

One-hot encoding requires only one bit set at a time. 3'b110 has two bits set, breaking the encoding and causing synthesis/runtime issues.

🧠 Conceptual

expert

Minimal bit width for Gray code FSM

You have a FSM with 10 states encoded using Gray code. What is the minimal number of bits required to encode all states uniquely?

A 4 bits

B 5 bits

C 3 bits

D 6 bits

💡 Hint

Think about how many unique states can be represented by n bits.

4 bits can represent 16 unique states, which is enough for 10 states. 3 bits only represent 8 states, which is insufficient.

Practice

1.

Which state encoding method uses exactly one bit set to 1 for each state, and all other bits are 0?

easy

A. One-hot encoding

B. Binary encoding

C. Gray encoding

D. Thermometer encoding

Solution

1. Step 1: Understand one-hot encoding definition

   One-hot encoding assigns a unique bit to each state, where only one bit is high (1) and the rest are low (0).

2. Step 2: Compare with other encodings

   Binary encoding uses multiple bits to represent states in binary form; Gray encoding changes only one bit between states; Thermometer encoding is different and not the one-hot method.

3. Final Answer:

   One-hot encoding -> Option A

4. Quick Check:

   One-hot = single 1 bit per state [OK]

Hint: One-hot means only one bit is 1 at a time [OK]

Common Mistakes:

• Confusing binary encoding with one-hot
• Thinking Gray encoding sets only one bit
• Mixing thermometer encoding with one-hot

2.

Which of the following is the correct Verilog declaration for a 3-bit binary encoded state register named state?

easy

A. reg state[2:0];

B. reg [3:0] state;

C. reg [2:0] state;

D. wire [2:0] state;

Solution

1. Step 1: Understand Verilog register declaration

   For a 3-bit register, the correct syntax is reg [2:0] name; where bits are indexed from 2 down to 0.

2. Step 2: Check options for correctness

   reg [2:0] state; uses reg [2:0] state; which is correct. reg [3:0] state; declares 4 bits, wire [2:0] state; uses wire (not register), and reg state[2:0]; has incorrect syntax.

3. Final Answer:

   reg [2:0] state; -> Option C

4. Quick Check:

   3-bit reg = reg [2:0] name [OK]

Hint: Use reg [N-1:0] for N-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for state storage
• Incorrect bit range syntax
• Confusing array declaration with bit vector

3.

Given the following Verilog snippet using one-hot encoding for 4 states, what is the value of state after the first clock cycle if the initial state is 4'b0001 and the next state logic shifts the 1 bit left by one position?

reg [3:0] state = 4'b0001;
always @(posedge clk) begin
  state <= {state[2:0], state[3]};
end

medium

A. 4'b0001

B. 4'b0100

C. 4'b1000

D. 4'b0010

Solution

1. Step 1: Understand the shift operation in the code

   The assignment state <= {state[2:0], state[3]}; shifts bits left by one, moving bit 0 to bit 1, bit 1 to bit 2, bit 2 to bit 3, and bit 3 to bit 0.

2. Step 2: Apply the shift to initial state 4'b0001

   Initial bits: bit3=0, bit2=0, bit1=0, bit0=1. After shift: bit3=bit2=0, bit2=bit1=0, bit1=bit0=1, bit0=bit3=0 -> 4'b0010.

3. Final Answer:

   4'b0010 -> Option D

4. Quick Check:

   Shift left one bit in one-hot = 4'b0010 [OK]

Hint: Shift bits left, wrap last bit to first [OK]

Common Mistakes:

• Forgetting bit wrap-around
• Confusing bit order in concatenation
• Assuming no change after clock

4.

Identify the error in the following Verilog code snippet that attempts to implement Gray code state encoding for 3 states:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state <= 2'b01;
    2'b01: state <= 2'b11;
    2'b11: state <= 2'b10;
    2'b10: state <= 2'b01;
    default: state <= 2'b00;
  endcase
end

medium

A. State transitions do not follow Gray code rules

B. State register width is too small for 3 states

C. Missing reset condition for state register

D. Using blocking assignment instead of non-blocking

Solution

1. Step 1: Check state transitions for Gray code property

   Gray code requires only one bit change between consecutive states. Check transitions: 00->01 (1 bit change), 01->11 (1 bit change), 11->10 (1 bit change), 10->01 (2 bits change).

2. Step 2: Identify violation in transitions

   The transition 10->01 changes two bits, violating Gray code rules.

3. Final Answer:

   State transitions do not follow Gray code rules -> Option A

4. Quick Check:

   Gray code = one bit change per transition [OK]

Hint: Gray code changes only one bit between states [OK]

Common Mistakes:

• Ignoring multi-bit changes in transitions
• Assuming register width is incorrect
• Confusing blocking and non-blocking assignments

5.

You need to design a finite state machine (FSM) with 8 states. Which state encoding method is best to minimize the number of flip-flops used, and why?

hard

A. One-hot encoding, because it uses fewer flip-flops

B. Binary encoding, because it uses the minimum number of flip-flops

C. Gray encoding, because it reduces glitches in output

D. Thermometer encoding, because it is simplest to implement

Solution

1. Step 1: Calculate flip-flops needed for each encoding

   For 8 states, binary encoding needs 3 flip-flops (2^3=8). One-hot encoding needs 8 flip-flops (one per state). Gray encoding also uses binary bits, so 3 flip-flops.

2. Step 2: Choose encoding minimizing flip-flops

   Binary encoding uses the fewest flip-flops (3) compared to one-hot (8). Gray encoding is similar to binary but mainly reduces glitches, not flip-flop count.

3. Final Answer:

   Binary encoding, because it uses the minimum number of flip-flops -> Option B

4. Quick Check:

   Binary encoding = minimum flip-flops for many states [OK]

Hint: Binary encoding uses log2(states) flip-flops [OK]

Common Mistakes:

• Choosing one-hot for fewer flip-flops
• Confusing glitch reduction with flip-flop count
• Assuming thermometer encoding is minimal