State encoding (binary, one-hot, gray) in Verilog - Time & Space Complexity

Time Complexity: State encoding (binary, one-hot, gray)

O(log n)

Understanding Time Complexity

When designing state machines in Verilog, the way states are encoded affects how many operations happen as the machine runs.

We want to see how the number of states changes the work done each clock cycle.

Scenario Under Consideration

Analyze the time complexity of this simple state machine using binary encoding.

module fsm_binary(
  input clk, reset,
  output reg [1:0] state
);
  always @(posedge clk or posedge reset) begin
    if (reset) state <= 2'b00;
    else state <= state + 1;
  end
endmodule

This code cycles through 4 states using binary counting on each clock tick.

Identify Repeating Operations

Look at what repeats as the input (number of states) grows.

• Primary operation: State update on each clock cycle.
• How many times: Once per clock cycle, but the complexity depends on how many bits represent the state.

How Execution Grows With Input

As the number of states doubles, the number of bits needed grows by one.

Number of States (n)	Bits Needed
4	2
8	3
16	4

Pattern observation: The bits grow slowly (logarithmically) as states increase, so the update work grows slowly too.

Final Time Complexity

Time Complexity: O(log n)

This means the work to update the state grows slowly as the number of states grows, because more bits are needed.

Common Mistake

[X] Wrong: "The state update takes the same time no matter how many states there are."

[OK] Correct: More states mean more bits to update, so the hardware must handle more signals, which takes more work.

Interview Connect

Understanding how state encoding affects update work helps you design efficient circuits and explain your choices clearly in interviews.

Self-Check

What if we changed from binary encoding to one-hot encoding? How would the time complexity change?