Why flip-flops are the basis of memory in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a D flip-flop with asynchronous reset.

Verilog

module dff (input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge [1]) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

Drag options to blanks, or click blank then click option'

Arst

Bclk

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock signal instead of reset in sensitivity list.

Forgetting to include reset in sensitivity list.

The asynchronous reset is triggered on the positive edge of the reset signal rst.

2fill in blank

medium

Complete the code to assign the output of the flip-flop.

Verilog

always @(posedge clk) begin
  q <= [1];
end

Drag options to blanks, or click blank then click option'

Arst

Bclk

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning clock or reset to output.

Assigning output to itself inside always block.

The flip-flop output q takes the value of the input d at the rising edge of the clock.

3fill in blank

hard

Fix the error in the sensitivity list to make the flip-flop work correctly.

Verilog

always @([1]) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Anegedge clk or posedge rst

Bnegedge rst

Cposedge clk

Dposedge clk or posedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using only clock or only reset in sensitivity list.

Using negative edge for reset instead of positive edge.

The flip-flop should respond to the positive edge of the clock and the positive edge of the reset signal.

4fill in blank

hard

Fill both blanks to create a flip-flop that stores data on the rising clock edge and resets asynchronously.

Verilog

always @([1] or [2]) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge clk

Cposedge rst

Dnegedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using falling edge for clock or reset.

Not including both signals in sensitivity list.

The flip-flop triggers on the rising edge of the clock and the rising edge of the reset signal for asynchronous reset.

5fill in blank

hard

Fill all three blanks to create a module that stores data on clock edge, resets asynchronously, and outputs the stored value.

Verilog

module dff (input [1], input [2], input d, output reg [3]);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

Drag options to blanks, or click blank then click option'

Aclk

Brst

Cq

Dd

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing input and output names.

Using data input name as output.

The module inputs are clock clk and reset rst. The output is the stored value q.

Practice

1. Why are flip-flops considered the basis of memory in digital circuits?

easy

A. Because they can store one bit of data on clock edges

B. Because they perform arithmetic operations

C. Because they generate clock signals

D. Because they convert analog signals to digital

Solution

1. Step 1: Understand flip-flop function

   Flip-flops store a single bit of data by capturing input on clock edges.

2. Step 2: Connect storage to memory concept

   Storing data over time is the key property needed for memory in digital circuits.

3. Final Answer:

   Because they can store one bit of data on clock edges -> Option A

4. Quick Check:

   Flip-flops store bits = D [OK]

Hint: Flip-flops store bits on clock edges, enabling memory [OK]

Common Mistakes:

• Confusing flip-flops with arithmetic units
• Thinking flip-flops generate clocks
• Assuming flip-flops convert analog signals

2. Which of the following is the correct Verilog syntax to declare a positive edge triggered D flip-flop storing input d into output q?

easy

A. always @(negedge clk) q = d;

B. always @(posedge clk) q = d + 1;

C. always @(clk) q <= d;

D. always @(posedge clk) q <= d;

Solution

1. Step 1: Identify correct clock edge sensitivity

   Positive edge triggered flip-flops use posedge clk in sensitivity list.

2. Step 2: Use non-blocking assignment for sequential logic

   Non-blocking assignment <= is used inside flip-flops to avoid race conditions.

3. Final Answer:

   always @(posedge clk) q <= d; -> Option D

4. Quick Check:

   Positive edge + non-blocking = B [OK]

Hint: Use 'always @(posedge clk)' with '<=' for flip-flops [OK]

Common Mistakes:

• Using blocking '=' instead of non-blocking '<='
• Using negedge instead of posedge for positive edge flip-flop
• Missing clock edge in sensitivity list

3. Given the Verilog code snippet:

reg q;
always @(posedge clk) begin
  q <= d;
end

If the input d is 1 at the rising edge of clk, what will be the value of q immediately after the clock edge?

medium

A. Unknown

B. 0

C. 1

D. It depends on the previous value of q

Solution

1. Step 1: Understand non-blocking assignment timing

   At the rising edge, q is scheduled to update to d value, which is 1.

2. Step 2: Determine value after clock edge

   Immediately after the clock edge, q becomes 1 as assigned by the flip-flop.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   d=1 at posedge clk means q=1 [OK]

Hint: Flip-flop output updates to input at clock edge [OK]

Common Mistakes:

• Thinking q updates before clock edge
• Assuming q keeps old value immediately after clock
• Confusing blocking and non-blocking assignments

4. Identify the error in this Verilog flip-flop code:

reg q;
always @(clk) begin
  q = d;
end

medium

A. Missing clock edge in sensitivity list

B. Using blocking assignment instead of non-blocking

C. No reset signal included

D. Output q should be wire, not reg

Solution

1. Step 1: Check sensitivity list for flip-flop

   Flip-flops must trigger on clock edges, e.g., posedge clk or negedge clk, not just clk.

2. Step 2: Confirm assignment type

   Blocking assignment = is discouraged but not a syntax error; main issue is sensitivity list.

3. Final Answer:

   Missing clock edge in sensitivity list -> Option A

4. Quick Check:

   Sensitivity must include clock edge [OK]

Hint: Use posedge/negedge in sensitivity list for flip-flops [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Ignoring non-blocking assignment best practice
• Confusing reg and wire for outputs

5. You want to build a 4-bit memory register using flip-flops in Verilog. Which approach correctly uses flip-flops to store the 4-bit input data_in on the rising edge of clk?

hard

A. Use combinational logic to latch data_in without clock

B. Use four separate flip-flops, each storing one bit of data_in with always @(posedge clk)

C. Use one flip-flop with 4-bit width and always @(clk) sensitivity

D. Use flip-flops triggered on falling edge to store data

Solution

1. Step 1: Understand flip-flop storage for multi-bit data

   Each flip-flop stores one bit; four flip-flops store 4 bits in parallel.

2. Step 2: Confirm correct clock edge and sensitivity

   Flip-flops must trigger on clock edges, typically posedge clk, to store data synchronously.

3. Final Answer:

   Use four separate flip-flops, each storing one bit of data_in with always @(posedge clk) -> Option B

4. Quick Check:

   One flip-flop per bit + posedge clk = C [OK]

Hint: Use one flip-flop per bit with posedge clk for registers [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Trying to store multi-bit data in one flip-flop incorrectly
• Using combinational logic instead of flip-flops for memory