Why flip-flops are the basis of memory in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a D flip-flop with asynchronous reset.

Verilog

module dff (input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge [1]) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

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Arst

Bclk

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock signal instead of reset in sensitivity list.

Forgetting to include reset in sensitivity list.

The asynchronous reset is triggered on the positive edge of the reset signal rst.

2fill in blank

medium

Complete the code to assign the output of the flip-flop.

Verilog

always @(posedge clk) begin
  q <= [1];
end

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Arst

Bclk

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning clock or reset to output.

Assigning output to itself inside always block.

The flip-flop output q takes the value of the input d at the rising edge of the clock.

3fill in blank

hard

Fix the error in the sensitivity list to make the flip-flop work correctly.

Verilog

always @([1]) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

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Anegedge clk or posedge rst

Bnegedge rst

Cposedge clk

Dposedge clk or posedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using only clock or only reset in sensitivity list.

Using negative edge for reset instead of positive edge.

The flip-flop should respond to the positive edge of the clock and the positive edge of the reset signal.

4fill in blank

hard

Fill both blanks to create a flip-flop that stores data on the rising clock edge and resets asynchronously.

Verilog

always @([1] or [2]) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

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Aposedge clk

Bnegedge clk

Cposedge rst

Dnegedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using falling edge for clock or reset.

Not including both signals in sensitivity list.

The flip-flop triggers on the rising edge of the clock and the rising edge of the reset signal for asynchronous reset.

5fill in blank

hard

Fill all three blanks to create a module that stores data on clock edge, resets asynchronously, and outputs the stored value.

Verilog

module dff (input [1], input [2], input d, output reg [3]);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

Drag options to blanks, or click blank then click option'

Aclk

Brst

Cq

Dd

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing input and output names.

Using data input name as output.

The module inputs are clock clk and reset rst. The output is the stored value q.