Why flip-flops are the basis of memory in Verilog - Challenge Your Understanding

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple D flip-flop module

What is the output Q after the positive edge of the clock if D=1 and initial Q=0?

Verilog

module d_flip_flop(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

// Initial Q=0, D=1, clk rising edge triggers update

A Q remains 0

B Q becomes 1

C Q becomes 0 then 1 immediately

D Q toggles between 0 and 1

💡 Hint

Remember that on the rising edge of clk, Q takes the value of D.

A D flip-flop captures the input D at the rising edge of the clock and holds it. Since D=1, Q updates to 1.

🧠 Conceptual

intermediate

Why flip-flops can store bits

Why can flip-flops store a single bit of information reliably?

A Because they reset automatically every clock cycle

B Because they use combinational logic only

C Because they have feedback loops that hold the output stable until changed

D Because they generate random outputs to store data

💡 Hint

Think about how the output stays the same between clock edges.

Flip-flops have feedback that keeps the output stable, so the stored bit remains until a new input changes it.

🔧 Debug

advanced

Identify the error in this flip-flop code

What error will this Verilog code cause when simulating a D flip-flop?

Verilog

module dff(input clk, input d, output reg q);
  always @(clk) begin
    if (clk == 1) q = d;
  end
endmodule

A It causes a latch inference due to missing edge sensitivity

B It works correctly as a D flip-flop

C It causes a syntax error because of missing semicolon

D It causes a runtime error due to wrong variable type

💡 Hint

Check the sensitivity list and how the clock is used.

Using @(clk) triggers on any clk change, not just rising edge, causing latch behavior instead of flip-flop.

🚀 Application

advanced

How many flip-flops are needed to store 8 bits?

If you want to store an 8-bit number using flip-flops, how many flip-flops do you need?

A 16 flip-flops, to store bits and parity

B 1 flip-flop, because it can store multiple bits

C 4 flip-flops, because each stores 2 bits

D 8 flip-flops, one for each bit

💡 Hint

Each flip-flop stores exactly one bit.

Each flip-flop stores one bit, so 8 bits require 8 flip-flops.

❓ Predict Output

expert

Output of a flip-flop chain storing a bit pattern

Given this Verilog code for a 3-bit shift register using D flip-flops, what is the output Q2 after three clock cycles if D inputs are 1, 0, 1 respectively?

Verilog

module shift_reg(input clk, input d, output reg q0, output reg q1, output reg q2);
  always @(posedge clk) begin
    q2 <= q1;
    q1 <= q0;
    q0 <= d;
  end
endmodule

// Initial q0=q1=q2=0, inputs on clk cycles: 1, then 0, then 1

A Q2 = 1

B Q2 = 0 then 1 immediately

C Q2 = 0

D Q2 = 1 then 0 immediately

💡 Hint

Trace the values of q0, q1, q2 step by step for each clock.

After three clock cycles, q2 holds the value of q1 from the previous cycle. The sequence is: Cycle 1: q0=1, q1=0, q2=0 Cycle 2: q0=0, q1=1, q2=0 Cycle 3: q0=1, q1=0, q2=1 (from q1 of cycle 2) So after the third clock, q2=1.