Why counters are fundamental in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit counter register.

Verilog

reg [[1]:0] counter;

Drag options to blanks, or click blank then click option'

A0

B3

C7

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 instead of 3 as the upper index.

Forgetting the range syntax.

The counter is 4 bits wide, so the index goes from 3 down to 0.

2fill in blank

medium

Complete the code to increment the counter on each clock cycle.

Verilog

always @(posedge clk) begin
  if (reset) counter <= 0;
  else counter <= counter [1] 1;
end

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A+

B-

C*

D/

Attempts:

3 left

💡 Hint

Common Mistakes

Using '-' which decreases the counter.

Using '*' or '/' which are not for incrementing.

The counter increases by 1 each clock cycle, so we use the plus operator.

3fill in blank

hard

Fix the error in the counter reset condition to make it synchronous.

Verilog

always @(posedge clk) begin
  if ([1]) counter <= 0;
  else counter <= counter + 1;
end

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Aenable

Bclk

Creset_n

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset_n' which is active low and may need negation.

Using 'clk' or 'enable' which are not reset signals.

The synchronous reset uses the 'reset' signal checked inside the clocked block.

4fill in blank

hard

Fill both blanks to create a modulo-10 counter that resets after 9.

Verilog

always @(posedge clk) begin
  if (reset) counter <= 0;
  else if (counter [1] 9) counter <= 0;
  else counter <= counter [2] 1;
end

Drag options to blanks, or click blank then click option'

A>

B<

C+

D-

Attempts:

3 left

💡 Hint

Common Mistakes

Using '<' which resets too early.

Using '-' which decreases the counter.

The counter resets when it is greater than 9, and increments by 1 otherwise.

5fill in blank

hard

Fill all three blanks to create a parameterized counter with enable and synchronous reset.

Verilog

module counter #(parameter WIDTH = [1]) (
  input clk,
  input reset,
  input [2],
  output reg [WIDTH-1:0] count
);

always @(posedge clk) begin
  if (reset) count <= 0;
  else if ([3]) count <= count + 1;
end
endmodule

Drag options to blanks, or click blank then click option'

A8

Benable

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using '1' as a signal name instead of 'enable'.

Confusing parameter and signal names.

The WIDTH parameter is set to 8 bits, the input signal is named 'enable', and the counter increments only when 'enable' is high.