Why counters are fundamental in Verilog - See It in Action

Why counters are fundamental

📖 Scenario: Imagine you want to count how many times a button is pressed on a device. Counters help us keep track of numbers in digital circuits, like counting events or timing actions.

🎯 Goal: You will build a simple 4-bit counter in Verilog that counts up on each clock pulse. This shows how counters work and why they are important in digital design.

📋 What You'll Learn

Create a 4-bit register called count to hold the counter value

Create a clock input called clk and a reset input called rst

On each rising edge of clk, increase count by 1 if rst is low

If rst is high, reset count to 0

Print the value of count after each clock cycle in simulation

💡 Why This Matters

🌍 Real World

Counters are used in devices like digital clocks, timers, and event counters to keep track of time or occurrences.

💼 Career

Understanding counters is essential for hardware engineers and anyone designing digital circuits or working with FPGA and ASIC development.

1

Create the counter register and inputs

Write a Verilog module named simple_counter with inputs clk and rst. Inside, declare a 4-bit register called count initialized to 0.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  // Your code here
endmodule

Hint

Use reg [3:0] count = 4'b0000; to create a 4-bit register starting at zero.

2

Add the reset and clock logic

Inside the simple_counter module, add an always block triggered on the rising edge of clk. Inside, if rst is high, set count to 0.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    // Your code here
  end
endmodule

Hint

Use always @(posedge clk) and inside check if (rst) to reset count.

3

Increment the counter on clock

Extend the always block so that if rst is low, count increases by 1 on each rising edge of clk.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    if (rst) begin
      count <= 4'b0000;
    end else begin
      // Your code here
    end
  end
endmodule

Hint

Use count <= count + 1; inside the else block to increment.

4

Simulate and display the counter value

Write a testbench module named testbench that creates a clock signal and reset signal. Run the clock for 10 cycles, toggle rst at start, and use $display to print count value each cycle.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    if (rst) begin
      count <= 4'b0000;
    end else begin
      count <= count + 1;
    end
  end
endmodule

module testbench();
  // Your code here
endmodule

Hint

Create a clock signal toggling every 5 units and use $monitor to print count. Release reset after 10 units.

Practice

1. Why are counters considered fundamental in digital circuit design?

easy

A. They generate random numbers for encryption.

B. They store large amounts of data permanently.

C. They convert analog signals to digital.

D. They keep track of events or time automatically.

Solution

1. Step 1: Understand the role of counters

   Counters are used to count events or measure time intervals automatically in digital circuits.

2. Step 2: Compare with other options

   The other options describe functions unrelated to counters: generating random numbers for encryption, storing large amounts of data permanently, and converting analog signals to digital.

3. Final Answer:

   They keep track of events or time automatically. -> Option D

4. Quick Check:

   Counters track events/time [OK]

Hint: Counters count events or time, not store or convert [OK]

Common Mistakes:

• Confusing counters with memory units
• Thinking counters generate random values
• Mixing counters with analog-to-digital converters

2. Which of the following is the correct Verilog syntax to declare a 4-bit counter register?

easy

A. reg [3:0] counter;

B. wire [4:0] counter;

C. int counter[3:0];

D. reg counter[4];

Solution

1. Step 1: Identify correct register declaration

   In Verilog, a 4-bit register is declared as reg [3:0] counter; where bits are indexed from 3 down to 0.

2. Step 2: Eliminate incorrect options

   wire [4:0] counter; uses wire instead of reg and wrong bit width (5 bits); int counter[3:0]; uses incorrect syntax for bit vectors; reg counter[4]; has wrong indexing and declares an unpacked array.

3. Final Answer:

   reg [3:0] counter; -> Option A

4. Quick Check:

   4-bit reg syntax [OK]

Hint: Use reg with [3:0] for 4-bit counters in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range indexing
• Confusing array syntax with bit vectors

3. What is the output of this Verilog code snippet for a 3-bit counter after 5 clock cycles?

reg [2:0] count = 3'b000;
always @(posedge clk) begin
  count <= count + 1;
end

medium

A. 3'b111

B. 3'b100

C. 3'b101

D. 3'b010

Solution

1. Step 1: Understand counter increment

   The counter starts at 0 and increments by 1 on each positive clock edge.

2. Step 2: Calculate count after 5 cycles

   After 5 increments: 0 + 5 = 5 decimal, which is 3'b101 in binary.

3. Final Answer:

   3'b101 -> Option C

4. Quick Check:

   0 + 5 = 5 decimal = 101 binary [OK]

Hint: Count increments by 1 each clock; convert decimal to binary [OK]

Common Mistakes:

• Off-by-one counting errors
• Confusing binary and decimal values
• Ignoring initial value of counter

4. Identify the error in this Verilog counter code:

reg [2:0] count;
always @(posedge clk) begin
  count = count + 1;
end

medium

A. Missing initial value for count

B. Using blocking assignment (=) instead of non-blocking (<=) inside always block

C. Incorrect bit width for count

D. Always block sensitivity list is incomplete

Solution

1. Step 1: Check assignment type in sequential logic

   Inside an always block triggered by clock edge, non-blocking assignment (<=) should be used to avoid race conditions.

2. Step 2: Verify other options

   Initial value is optional; bit width is correct; sensitivity list with posedge clk is proper.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option B

4. Quick Check:

   Use <= for sequential logic assignments [OK]

Hint: Use <= in always @(posedge clk) blocks for counters [OK]

Common Mistakes:

• Using = instead of <= in clocked always blocks
• Assuming initial value is mandatory
• Misunderstanding sensitivity list requirements

5. You want to design a 4-bit counter that resets to zero after reaching 9 (decimal). Which Verilog code snippet correctly implements this behavior?

hard

A. reg [3:0] count;
always @(posedge clk or posedge reset) begin
if (reset)
count <= 0;
else if (count == 4'd9)
count <= 0;
else
count <= count + 1;
end

B. reg [3:0] count;
always @(posedge clk) begin
if (count == 4'd10)
count <= 0;
else
count <= count + 1;
end

C. reg [3:0] count;
always @(posedge clk) begin
if (count >= 9)
count = 0;
else
count = count + 1;
end

D. reg [3:0] count;
always @(posedge clk) begin
count <= count + 1;
if (count == 4'd9)
count <= 0;
end

Solution

1. Step 1: Check reset and counting logic

   reg [3:0] count;
   always @(posedge clk or posedge reset) begin
     if (reset)
       count <= 0;
     else if (count == 4'd9)
       count <= 0;
     else
       count <= count + 1;
   end

   includes asynchronous reset and resets count to 0 when count reaches 9, then counts up correctly.

2. Step 2: Analyze other options for correctness

   The snippet resetting at 4'd10 lacks reset signal and uses wrong threshold; the one using blocking assignments and >= 9 condition has simulation order issues; the one incrementing then conditionally resetting causes multiple drivers and races.

3. Final Answer:

   Code with async reset, check count == 4'd9, non-blocking assignments -> Option A

4. Quick Check:

   Reset at 9 with <= and reset signal [OK]

Hint: Reset counter at max value with non-blocking and reset signal [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting at wrong count value
• Ignoring asynchronous reset signal
• Updating and resetting count in wrong order