Why counters are fundamental in Verilog - See It in Action

Why counters are fundamental

📖 Scenario: Imagine you want to count how many times a button is pressed on a device. Counters help us keep track of numbers in digital circuits, like counting events or timing actions.

🎯 Goal: You will build a simple 4-bit counter in Verilog that counts up on each clock pulse. This shows how counters work and why they are important in digital design.

📋 What You'll Learn

Create a 4-bit register called count to hold the counter value

Create a clock input called clk and a reset input called rst

On each rising edge of clk, increase count by 1 if rst is low

If rst is high, reset count to 0

Print the value of count after each clock cycle in simulation

💡 Why This Matters

🌍 Real World

Counters are used in devices like digital clocks, timers, and event counters to keep track of time or occurrences.

💼 Career

Understanding counters is essential for hardware engineers and anyone designing digital circuits or working with FPGA and ASIC development.

1

Create the counter register and inputs

Write a Verilog module named simple_counter with inputs clk and rst. Inside, declare a 4-bit register called count initialized to 0.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  // Your code here
endmodule

Need a hint?

Use reg [3:0] count = 4'b0000; to create a 4-bit register starting at zero.

2

Add the reset and clock logic

Inside the simple_counter module, add an always block triggered on the rising edge of clk. Inside, if rst is high, set count to 0.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    // Your code here
  end
endmodule

Need a hint?

Use always @(posedge clk) and inside check if (rst) to reset count.

3

Increment the counter on clock

Extend the always block so that if rst is low, count increases by 1 on each rising edge of clk.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    if (rst) begin
      count <= 4'b0000;
    end else begin
      // Your code here
    end
  end
endmodule

Need a hint?

Use count <= count + 1; inside the else block to increment.

4

Simulate and display the counter value

Write a testbench module named testbench that creates a clock signal and reset signal. Run the clock for 10 cycles, toggle rst at start, and use $display to print count value each cycle.

Verilog

module simple_counter(input clk, input rst);
  reg [3:0] count = 4'b0000;
  always @(posedge clk) begin
    if (rst) begin
      count <= 4'b0000;
    end else begin
      count <= count + 1;
    end
  end
endmodule

module testbench();
  // Your code here
endmodule

Need a hint?

Create a clock signal toggling every 5 units and use $monitor to print count. Release reset after 10 units.