Why always blocks are needed in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to create a simple always block that triggers on the positive edge of the clock.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aclk

Bnegedge clk

Cposedge clk

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' without edge specification causes continuous triggering.

Using 'posedge reset' triggers on reset, not clock.

The always block triggers on the positive edge of the clock signal, which is common for synchronous logic.

2fill in blank

medium

Complete the always block sensitivity list to trigger on both positive edge of clk and negative edge of reset.

Verilog

always @([1]) begin
  if (!reset_n)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk and negedge reset_n

Bposedge clk or negedge reset_n

Cposedge clk, posedge reset_n

Dnegedge clk or posedge reset_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Using posedge for active low reset signal.

The always block triggers on the positive edge of clk or the negative edge of reset_n to asynchronously reset the output.

3fill in blank

hard

Fix the error in the always block to correctly model a D flip-flop with asynchronous reset.

Verilog

always @([1]) begin
  if (reset)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or posedge reset

Bposedge clk and posedge reset

Cclk or reset

Dnegedge clk or posedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Missing reset edge in sensitivity list.

The sensitivity list must include posedge clk and posedge reset to model asynchronous reset correctly.

4fill in blank

hard

Fill both blanks to create a combinational always block that updates output 'y' based on inputs 'a' and 'b'.

Verilog

always @([1]) begin
  y = a [2] b;
end

Drag options to blanks, or click blank then click option'

A*

Ba or b

C+

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge clk' in combinational block sensitivity list.

Using '*' instead of '+' for addition.

The sensitivity list for combinational logic uses 'a or b'. The operation '+' adds the inputs.

5fill in blank

hard

Fill all three blanks to create a synchronous counter that increments on clock's positive edge and resets asynchronously.

Verilog

always @([1]) begin
  if ([2])
    count <= 0;
  else
    count <= count [3] 1;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or posedge reset

Breset

C+

Dnegedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge reset when reset is active high.

Forgetting to include reset in sensitivity list.

The always block triggers on posedge clk or posedge reset. The reset condition checks 'reset'. The counter increments by adding 1.

Practice

1. Why are always blocks needed in Verilog?

easy

A. To describe behavior that changes over time or on signal events

B. To declare variables and constants

C. To include comments in the code

D. To define the module interface

Solution

1. Step 1: Understand the purpose of always blocks

   always blocks run code when signals change or on clock edges, allowing us to model hardware behavior that depends on time or events.

2. Step 2: Compare with other Verilog constructs

   Other constructs like module define interfaces, and comments or declarations do not describe changing behavior.

3. Final Answer:

   To describe behavior that changes over time or on signal events -> Option A

4. Quick Check:

   Always blocks = describe changing behavior [OK]

Hint: Always blocks run on signal changes or clocks [OK]

Common Mistakes:

• Thinking always blocks declare variables
• Confusing always blocks with module declarations
• Believing always blocks are for comments

2. Which of the following is the correct syntax to start an always block that triggers on the positive edge of a clock signal clk?

easy

A. always @(negedge clk) begin

B. always @(clk) begin

C. always @(posedge clk) begin

D. always @(clk == 1) begin

Solution

1. Step 1: Identify the correct event control syntax

   The correct syntax to trigger on the rising edge of a clock is always @(posedge clk).

2. Step 2: Check other options for correctness

   always @(clk) triggers on any change, negedge clk triggers on falling edge, and clk == 1 is invalid syntax.

3. Final Answer:

   always @(posedge clk) begin -> Option C

4. Quick Check:

   posedge clk = always @(posedge clk) [OK]

Hint: Use posedge/negedge for clock edges in always blocks [OK]

Common Mistakes:

• Using @(clk) instead of @(posedge clk)
• Writing conditions like @(clk == 1) which is invalid
• Confusing posedge with negedge

3. What will be the output of the following Verilog code snippet?

reg a = 0;
reg b;
always @(a) begin
  b = ~a;
end
initial begin
  a = 1;
  #1 $display("b = %b", b);
end

medium

A. b = 1

B. b = 0

C. b = x (unknown)

D. No output

Solution

1. Step 1: Understand the always block trigger and assignment

   The always block triggers when a changes. Initially, a is 0, then set to 1. When a changes to 1, b is assigned ~a, which is 0.

2. Step 2: Check the timing of $display

   The display happens after 1 time unit (#1), so b has been updated to ~1 = 0. But since b is assigned ~a, and a is 1, b is 0.

3. Final Answer:

   b = 0 -> Option B

4. Quick Check:

   b = ~a = 0 when a=1 [OK]

Hint: Always blocks update outputs on input changes [OK]

Common Mistakes:

• Assuming b stays at initial value
• Confusing timing of assignments and display
• Ignoring that always triggers on a change

4. Identify the error in this Verilog code snippet:

reg q;
always @(posedge clk) q = d;
always @(posedge clk) q = ~q;

medium

A. No error, code is correct

B. Missing semicolon after q = d

C. Incorrect sensitivity list syntax

D. Multiple always blocks driving the same signal cause conflict

Solution

1. Step 1: Analyze signal assignments in always blocks

   Both always blocks assign to the same signal q on the same clock edge, causing multiple drivers which is illegal in Verilog.

2. Step 2: Check syntax and sensitivity lists

   Semicolons and sensitivity lists are correct, so no syntax errors there.

3. Final Answer:

   Multiple always blocks driving the same signal cause conflict -> Option D

4. Quick Check:

   One signal, multiple drivers = conflict [OK]

Hint: One signal should be assigned in only one always block [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking syntax errors cause the problem
• Assuming multiple always blocks can drive same reg

5. You want to model a flip-flop with asynchronous reset in Verilog. Which always block header correctly triggers on clock's rising edge and asynchronous reset signal rst?

hard

A. always @(posedge clk or posedge rst)

B. always @(posedge clk and posedge rst)

C. always @(clk or rst)

D. always @(posedge clk)

Solution

1. Step 1: Understand asynchronous reset triggering

   An asynchronous reset triggers immediately when rst changes, independent of clock. So the sensitivity list must include posedge rst along with posedge clk.

2. Step 2: Check syntax for multiple events

   The correct syntax uses or to combine events: always @(posedge clk or posedge rst). Using and or just clk or rst is incorrect.

3. Final Answer:

   always @(posedge clk or posedge rst) -> Option A

4. Quick Check:

   Async reset = posedge clk or posedge rst [OK]

Hint: Use 'or' to combine clock and async reset in always block [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using level-sensitive instead of edge-sensitive triggers