Why always blocks are needed in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to create a simple always block that triggers on the positive edge of the clock.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aclk

Bnegedge clk

Cposedge clk

Dposedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' without edge specification causes continuous triggering.

Using 'posedge reset' triggers on reset, not clock.

The always block triggers on the positive edge of the clock signal, which is common for synchronous logic.

2fill in blank

medium

Complete the always block sensitivity list to trigger on both positive edge of clk and negative edge of reset.

Verilog

always @([1]) begin
  if (!reset_n)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk and negedge reset_n

Bposedge clk or negedge reset_n

Cposedge clk, posedge reset_n

Dnegedge clk or posedge reset_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Using posedge for active low reset signal.

The always block triggers on the positive edge of clk or the negative edge of reset_n to asynchronously reset the output.

3fill in blank

hard

Fix the error in the always block to correctly model a D flip-flop with asynchronous reset.

Verilog

always @([1]) begin
  if (reset)
    q <= 0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or posedge reset

Bposedge clk and posedge reset

Cclk or reset

Dnegedge clk or posedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Missing reset edge in sensitivity list.

The sensitivity list must include posedge clk and posedge reset to model asynchronous reset correctly.

4fill in blank

hard

Fill both blanks to create a combinational always block that updates output 'y' based on inputs 'a' and 'b'.

Verilog

always @([1]) begin
  y = a [2] b;
end

Drag options to blanks, or click blank then click option'

A*

Ba or b

C+

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge clk' in combinational block sensitivity list.

Using '*' instead of '+' for addition.

The sensitivity list for combinational logic uses 'a or b'. The operation '+' adds the inputs.

5fill in blank

hard

Fill all three blanks to create a synchronous counter that increments on clock's positive edge and resets asynchronously.

Verilog

always @([1]) begin
  if ([2])
    count <= 0;
  else
    count <= count [3] 1;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or posedge reset

Breset

C+

Dnegedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge reset when reset is active high.

Forgetting to include reset in sensitivity list.

The always block triggers on posedge clk or posedge reset. The reset condition checks 'reset'. The counter increments by adding 1.