Why always blocks are needed in Verilog - See It in Action

Understanding Why Always Blocks Are Needed in Verilog

📖 Scenario: Imagine you are designing a simple digital circuit that turns on a light when a button is pressed. You want the circuit to react automatically whenever the button changes state.

🎯 Goal: You will create a Verilog module that uses an always block to detect changes in the button input and control the light output accordingly. This will help you understand why always blocks are needed to describe behavior that depends on changes in signals.

📋 What You'll Learn

Create a Verilog module with input button and output light

Declare light as a reg type

Use an always block triggered on changes to button

Inside the always block, assign light the value of button

Add a testbench to simulate pressing and releasing the button

Print the value of light after each change

💡 Why This Matters

🌍 Real World

Digital circuits like switches and lights need to respond instantly to input changes. Always blocks let hardware designers describe this reactive behavior clearly.

💼 Career

Understanding always blocks is fundamental for hardware engineers and FPGA developers who write Verilog to design and test digital systems.

1

Create the Verilog module with input and output

Write a Verilog module named ButtonLight with an input button and an output light. Declare light as a reg type.

Verilog

module ButtonLight(input button, output reg light);

// Your code here

endmodule

Need a hint?

Start by declaring the module and its ports. Remember to declare light as reg because it will be assigned inside an always block.

2

Add an always block triggered on button changes

Inside the ButtonLight module, add an always block that triggers on any change of button using always @(button).

Verilog

module ButtonLight(input button, output reg light);

// Add always block triggered on button changes

// Your code here

endmodule

Need a hint?

The always block runs whenever button changes. This lets the circuit react immediately.

3

Assign light inside the always block

Inside the always @(button) block, assign the value of button to light using a blocking assignment =.

Verilog

module ButtonLight(input button, output reg light);

    always @(button) begin
        // Assign light to button value
        // Your code here
    end

endmodule

Need a hint?

Inside the always block, assign light the current value of button. This models the light turning on or off with the button.

4

Create a testbench to simulate and print output

Write a testbench module named Testbench that declares a reg button and a wire light. Instantiate ButtonLight with these signals. Change button from 0 to 1 and back with delays, and use $display to print light after each change.

Verilog

module ButtonLight(input button, output reg light);

    always @(button) begin
        light = button;
    end

endmodule

// Your testbench code here

Need a hint?

The testbench changes button and prints light to show how the always block updates the output automatically.