Why always blocks are needed in Verilog - See It in Action

Understanding Why Always Blocks Are Needed in Verilog

📖 Scenario: Imagine you are designing a simple digital circuit that turns on a light when a button is pressed. You want the circuit to react automatically whenever the button changes state.

🎯 Goal: You will create a Verilog module that uses an always block to detect changes in the button input and control the light output accordingly. This will help you understand why always blocks are needed to describe behavior that depends on changes in signals.

📋 What You'll Learn

Create a Verilog module with input button and output light

Declare light as a reg type

Use an always block triggered on changes to button

Inside the always block, assign light the value of button

Add a testbench to simulate pressing and releasing the button

Print the value of light after each change

💡 Why This Matters

🌍 Real World

Digital circuits like switches and lights need to respond instantly to input changes. Always blocks let hardware designers describe this reactive behavior clearly.

💼 Career

Understanding always blocks is fundamental for hardware engineers and FPGA developers who write Verilog to design and test digital systems.

1

Create the Verilog module with input and output

Write a Verilog module named ButtonLight with an input button and an output light. Declare light as a reg type.

Verilog

module ButtonLight(input button, output reg light);

// Your code here

endmodule

Hint

Start by declaring the module and its ports. Remember to declare light as reg because it will be assigned inside an always block.

2

Add an always block triggered on button changes

Inside the ButtonLight module, add an always block that triggers on any change of button using always @(button).

Verilog

module ButtonLight(input button, output reg light);

// Add always block triggered on button changes

// Your code here

endmodule

Hint

The always block runs whenever button changes. This lets the circuit react immediately.

3

Assign light inside the always block

Inside the always @(button) block, assign the value of button to light using a blocking assignment =.

Verilog

module ButtonLight(input button, output reg light);

    always @(button) begin
        // Assign light to button value
        // Your code here
    end

endmodule

Hint

Inside the always block, assign light the current value of button. This models the light turning on or off with the button.

4

Create a testbench to simulate and print output

Write a testbench module named Testbench that declares a reg button and a wire light. Instantiate ButtonLight with these signals. Change button from 0 to 1 and back with delays, and use $display to print light after each change.

Verilog

module ButtonLight(input button, output reg light);

    always @(button) begin
        light = button;
    end

endmodule

// Your testbench code here

Hint

The testbench changes button and prints light to show how the always block updates the output automatically.

Practice

1. Why are always blocks needed in Verilog?

easy

A. To describe behavior that changes over time or on signal events

B. To declare variables and constants

C. To include comments in the code

D. To define the module interface

Solution

1. Step 1: Understand the purpose of always blocks

   always blocks run code when signals change or on clock edges, allowing us to model hardware behavior that depends on time or events.

2. Step 2: Compare with other Verilog constructs

   Other constructs like module define interfaces, and comments or declarations do not describe changing behavior.

3. Final Answer:

   To describe behavior that changes over time or on signal events -> Option A

4. Quick Check:

   Always blocks = describe changing behavior [OK]

Hint: Always blocks run on signal changes or clocks [OK]

Common Mistakes:

• Thinking always blocks declare variables
• Confusing always blocks with module declarations
• Believing always blocks are for comments

2. Which of the following is the correct syntax to start an always block that triggers on the positive edge of a clock signal clk?

easy

A. always @(negedge clk) begin

B. always @(clk) begin

C. always @(posedge clk) begin

D. always @(clk == 1) begin

Solution

1. Step 1: Identify the correct event control syntax

   The correct syntax to trigger on the rising edge of a clock is always @(posedge clk).

2. Step 2: Check other options for correctness

   always @(clk) triggers on any change, negedge clk triggers on falling edge, and clk == 1 is invalid syntax.

3. Final Answer:

   always @(posedge clk) begin -> Option C

4. Quick Check:

   posedge clk = always @(posedge clk) [OK]

Hint: Use posedge/negedge for clock edges in always blocks [OK]

Common Mistakes:

• Using @(clk) instead of @(posedge clk)
• Writing conditions like @(clk == 1) which is invalid
• Confusing posedge with negedge

3. What will be the output of the following Verilog code snippet?

reg a = 0;
reg b;
always @(a) begin
  b = ~a;
end
initial begin
  a = 1;
  #1 $display("b = %b", b);
end

medium

A. b = 1

B. b = 0

C. b = x (unknown)

D. No output

Solution

1. Step 1: Understand the always block trigger and assignment

   The always block triggers when a changes. Initially, a is 0, then set to 1. When a changes to 1, b is assigned ~a, which is 0.

2. Step 2: Check the timing of $display

   The display happens after 1 time unit (#1), so b has been updated to ~1 = 0. But since b is assigned ~a, and a is 1, b is 0.

3. Final Answer:

   b = 0 -> Option B

4. Quick Check:

   b = ~a = 0 when a=1 [OK]

Hint: Always blocks update outputs on input changes [OK]

Common Mistakes:

• Assuming b stays at initial value
• Confusing timing of assignments and display
• Ignoring that always triggers on a change

4. Identify the error in this Verilog code snippet:

reg q;
always @(posedge clk) q = d;
always @(posedge clk) q = ~q;

medium

A. No error, code is correct

B. Missing semicolon after q = d

C. Incorrect sensitivity list syntax

D. Multiple always blocks driving the same signal cause conflict

Solution

1. Step 1: Analyze signal assignments in always blocks

   Both always blocks assign to the same signal q on the same clock edge, causing multiple drivers which is illegal in Verilog.

2. Step 2: Check syntax and sensitivity lists

   Semicolons and sensitivity lists are correct, so no syntax errors there.

3. Final Answer:

   Multiple always blocks driving the same signal cause conflict -> Option D

4. Quick Check:

   One signal, multiple drivers = conflict [OK]

Hint: One signal should be assigned in only one always block [OK]

Common Mistakes:

• Ignoring multiple drivers on one signal
• Thinking syntax errors cause the problem
• Assuming multiple always blocks can drive same reg

5. You want to model a flip-flop with asynchronous reset in Verilog. Which always block header correctly triggers on clock's rising edge and asynchronous reset signal rst?

hard

A. always @(posedge clk or posedge rst)

B. always @(posedge clk and posedge rst)

C. always @(clk or rst)

D. always @(posedge clk)

Solution

1. Step 1: Understand asynchronous reset triggering

   An asynchronous reset triggers immediately when rst changes, independent of clock. So the sensitivity list must include posedge rst along with posedge clk.

2. Step 2: Check syntax for multiple events

   The correct syntax uses or to combine events: always @(posedge clk or posedge rst). Using and or just clk or rst is incorrect.

3. Final Answer:

   always @(posedge clk or posedge rst) -> Option A

4. Quick Check:

   Async reset = posedge clk or posedge rst [OK]

Hint: Use 'or' to combine clock and async reset in always block [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using level-sensitive instead of edge-sensitive triggers