Memory initialization with $readmemh in Verilog - Mini Project: Build & Apply

Memory initialization with $readmemh

📖 Scenario: You are designing a simple memory module in Verilog. You want to load initial data into the memory from a file using the $readmemh system task. This is useful when you want your memory to start with known values, like a small program or data table.

🎯 Goal: Build a Verilog module that declares a memory array and initializes it with values from a hex file using $readmemh. Then, display the loaded memory contents.

📋 What You'll Learn

Declare a memory array of 8 elements, each 8 bits wide.

Use $readmemh to load data from a file named memory_init.hex.

Display the memory contents after initialization using a for loop.

Use a testbench to run the initialization and display.

💡 Why This Matters

🌍 Real World

Memory initialization is common in FPGA and ASIC designs to preload programs or data tables before running hardware simulations or actual hardware.

💼 Career

Understanding how to initialize memory with <code>$readmemh</code> is important for hardware engineers working on embedded systems, firmware loading, and testbench creation.

1

Declare the memory array

Declare a memory array called mem with 8 elements, each 8 bits wide.

Verilog

// Declare memory array mem with 8 elements of 8 bits
// Your code here

Need a hint?

Use reg [7:0] mem [0:7]; to declare 8 elements of 8 bits each.

2

Add memory initialization with $readmemh

Inside an initial block, use $readmemh to load data from the file memory_init.hex into the memory array mem.

Verilog

reg [7:0] mem [0:7];

initial begin
    // Use $readmemh to load memory_init.hex into mem
    // Your code here
end

Need a hint?

Use $readmemh("memory_init.hex", mem); inside an initial block.

3

Display the memory contents

Inside the same initial block, add a for loop with variable i from 0 to 7 to display each memory element using $display in the format: mem[i] = value.

Verilog

reg [7:0] mem [0:7];

initial begin
    $readmemh("memory_init.hex", mem);
    
    // Display memory contents using for loop
    // Your code here
end

Need a hint?

Use a for loop with an integer i and $display to print each element.

4

Run the simulation and observe output

Run the simulation to see the memory contents printed. Use $finish after displaying all elements to end the simulation.

Verilog

reg [7:0] mem [0:7];

initial begin
    $readmemh("memory_init.hex", mem);
    
    integer i;
    for (i = 0; i < 8; i = i + 1) begin
        $display("mem[%0d] = %h", i, mem[i]);
    end
    
    // End simulation
    // Your code here
end

Need a hint?

Use $finish; to stop the simulation after printing.