Memory initialization with $readmemh in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog memory initialization?

Given the following Verilog code snippet, what will be the value of mem[2] after initialization?

Verilog

module test;
  reg [7:0] mem [0:3];
  initial begin
    $readmemh("data.hex", mem);
  end
endmodule

// Contents of data.hex:
// 0A
// 1B
// 2C
// 3D

A 8'h1B

B 8'h3D

C 8'h2C

D 8'h0A

💡 Hint

Remember that $readmemh loads data line by line starting at index 0.

The file data.hex has four lines: 0A, 1B, 2C, 3D. These are loaded into mem[0] to mem[3] respectively. So mem[2] gets the third line, which is 2C.

🧠 Conceptual

intermediate

How does $readmemh interpret the input file?

Which statement best describes how $readmemh initializes memory from a file?

A It reads hexadecimal values line by line and stores them sequentially starting at the specified memory address.

B It reads binary values separated by spaces and stores them randomly in memory.

C It reads decimal values and stores them in reverse order in memory.

D It reads ASCII characters and stores their decimal codes in memory.

💡 Hint

Think about the format of the file and how memory addresses are assigned.

$readmemh reads the file line by line, interpreting each line as a hexadecimal value, and stores each value sequentially starting at the first memory address.

🔧 Debug

advanced

Why does this $readmemh initialization fail?

Consider this Verilog code snippet:

reg [7:0] mem [0:3];
initial begin
  $readmemh("data.hex", mem, 1, 4);
end

The file data.hex contains 4 lines of hex data. What is the problem with this code?

A The $readmemh call must not include start and end addresses.

B The ending address 4 is out of bounds for mem[0:3], causing an error.

C The memory array must be declared as <code>reg [3:0] mem [0:7]</code> for $readmemh to work.

D The file name must be an absolute path, not a relative one.

💡 Hint

Check the memory array size and the range specified in $readmemh.

The memory array mem has indices 0 to 3. Specifying an end address of 4 exceeds the array bounds, which causes an error or undefined behavior.

📝 Syntax

advanced

Identify the syntax error in this $readmemh usage

What is wrong with this Verilog code snippet?

reg [7:0] mem [0:3];
initial begin
  $readmemh(data.hex, mem);
end

A The $readmemh function requires a third argument specifying the start address.

B The memory array must be declared as <code>wire</code>, not <code>reg</code>.

C The <code>initial</code> block must be replaced with an <code>always</code> block.

D The file name must be a string literal enclosed in double quotes.

💡 Hint

Look carefully at how the file name is passed to $readmemh.

The file name argument to $readmemh must be a string literal enclosed in double quotes. Without quotes, it is treated as an identifier, causing a syntax error.

🚀 Application

expert

How many memory locations are initialized by this $readmemh call?

Given the following code and file, how many memory locations in mem will be initialized?

reg [15:0] mem [0:7];
initial begin
  $readmemh("data.hex", mem, 2, 5);
end

// data.hex contains 8 lines of hex values.

A 4

B 6

C 8

D 5

💡 Hint

Count the number of addresses from start to end inclusive.

The call initializes memory from address 2 to 5 inclusive, which is 4 locations: 2, 3, 4, and 5.