Entity-Architecture model in VHDL - Step-by-Step Execution

Concept Flow - Entity-Architecture model

Start

↓

Define Entity

↓

Declare Ports

↓

Define Architecture

↓

Describe Behavior

↓

End Architecture

↓

Simulation or Synthesis

The flow starts by defining the entity with its ports, then the architecture describes the behavior, ending with simulation or synthesis.

Execution Sample

VHDL

entity AND_Gate is
  port(A, B: in std_logic;
       Y: out std_logic);
end AND_Gate;

architecture Behavioral of AND_Gate is
begin
  Y <= A and B;
end Behavioral;

This code defines an AND gate entity with inputs A, B and output Y, then describes its behavior in the architecture.

Execution Table

Step	Action	Entity Ports	Architecture Behavior	Output Y
1	Define entity AND_Gate with ports A, B (input), Y (output)	A: in, B: in, Y: out	Not started	Undefined
2	Start architecture Behavioral	Ports unchanged	Begin process	Undefined
3	Assign Y <= A and B	Ports unchanged	Y is assigned logical AND of A and B	Depends on A and B
4	Test with A='0', B='0'	A='0', B='0'	Y <= '0' and '0'	Y='0'
5	Test with A='0', B='1'	A='0', B='1'	Y <= '0' and '1'	Y='0'
6	Test with A='1', B='0'	A='1', B='0'	Y <= '1' and '0'	Y='0'
7	Test with A='1', B='1'	A='1', B='1'	Y <= '1' and '1'	Y='1'
8	End architecture	Ports unchanged	Behavior defined	Final output depends on inputs

💡 All input combinations tested; output Y reflects logical AND of inputs A and B.

Variable Tracker

Variable	Start	After Step 4	After Step 5	After Step 6	After Step 7	Final
A	Undefined	'0'	'0'	'1'	'1'	Varies
B	Undefined	'0'	'1'	'0'	'1'	Varies
Y	Undefined	'0'	'0'	'0'	'1'	Depends on A and B

Key Moments - 3 Insights

Why do we separate entity and architecture in VHDL?

Entity defines the interface (inputs/outputs), architecture defines the behavior. This separation allows reusing the same interface with different behaviors (see execution_table steps 1 and 3).

What happens if we change inputs A and B?

The output Y changes immediately according to the logic in architecture (see execution_table steps 4 to 7 showing output changes).

Can an entity have multiple architectures?

Yes, multiple architectures can describe different behaviors for the same entity interface, allowing flexible design reuse.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output Y when A=1 and B=0?

A Y=0

B Y=1

C Y=Undefined

D Y=Error

💡 Hint

Check execution_table row 6 where A=1 and B=0, output Y is 0.

At which step does the architecture start assigning output Y?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

See execution_table step 3 where Y is assigned as A and B.

If we add a new input C to the entity, how would the output Y assignment change?

A Y <= A xor B;

B Y <= A or B;

C Y <= A and B and C;

D No change needed

💡 Hint

Adding input C means output depends on A, B, and C; see architecture behavior in execution_table step 3.

Concept Snapshot

Entity-Architecture model in VHDL:
- Entity declares interface (inputs/outputs)
- Architecture describes behavior
- Ports connect entity and architecture
- Multiple architectures possible per entity
- Behavior defined by signal assignments inside architecture

Full Transcript

The Entity-Architecture model in VHDL separates the design into two parts: the entity defines the inputs and outputs, like a plug shape, and the architecture describes what the design does with those inputs to produce outputs. The example shows an AND gate entity with inputs A and B and output Y. The architecture assigns Y as the logical AND of A and B. The execution table traces how different input values affect output Y. This separation helps reuse and clarity in hardware design.

Practice

1. What is the main purpose of the entity in a VHDL design?

easy

A. To define the inputs and outputs of the circuit

B. To describe the internal behavior of the circuit

C. To specify the timing constraints

D. To declare variables used inside the circuit

Solution

1. Step 1: Understand the role of entity

   The entity defines the interface of the circuit, which means it lists all inputs and outputs.

2. Step 2: Differentiate from architecture

   The architecture describes how the circuit works inside, not the interface.

3. Final Answer:

   To define the inputs and outputs of the circuit -> Option A

4. Quick Check:

   Entity = Interface (inputs/outputs) [OK]

Hint: Entity = inputs and outputs, architecture = behavior [OK]

Common Mistakes:

• Confusing entity with architecture
• Thinking entity describes behavior
• Mixing interface with internal logic

2. Which of the following is the correct way to start an entity declaration in VHDL?

easy

A. entity design begin

B. architecture entity_name of design is

C. entity design is

D. architecture design is

Solution

1. Step 1: Recall entity declaration syntax

   The correct syntax to start an entity is: entity design_name is.

2. Step 2: Check options

   entity design is matches the correct syntax exactly. Other options confuse architecture and entity keywords or miss 'is'.

3. Final Answer:

   entity design is -> Option C

4. Quick Check:

   Entity declaration starts with 'entity name is' [OK]

Hint: Entity declaration always uses 'entity name is' [OK]

Common Mistakes:

• Using 'begin' instead of 'is' in entity
• Confusing entity and architecture keywords
• Starting entity with architecture keyword

3. Given the following VHDL code snippet, what is the output on out_signal when in_signal is '1'?

entity simple is
  port(in_signal : in std_logic; out_signal : out std_logic);
end simple;

architecture behavior of simple is
begin
  process(in_signal)
  begin
    if in_signal = '1' then
      out_signal <= '0';
    else
      out_signal <= '1';
    end if;
  end process;
end behavior;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Analyze the process behavior

   The process triggers on changes to in_signal. If in_signal is '1', out_signal is assigned '0'.

2. Step 2: Apply input value

   Given in_signal = '1', the condition is true, so out_signal becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Input '1' sets output '0' [OK]

Hint: Trace input through if condition to find output [OK]

Common Mistakes:

• Assuming output equals input directly
• Ignoring else branch
• Confusing signal assignment timing

4. Identify the error in the following VHDL code snippet:

entity test is
  port(a : in std_logic; b : out std_logic);
end test;

architecture arch of test is
begin
  process(a)
  begin
    if a = '1' then
      b <= '1'
    else
      b <= '0';
    end if;
  end process;
end arch;

medium

A. Missing semicolon after b <= '1'

B. Entity name does not match architecture name

C. Process sensitivity list is empty

D. Port directions are incorrect

Solution

1. Step 1: Check syntax inside process

   After b <= '1' there is no semicolon, which is required to end the statement.

2. Step 2: Verify other parts

   Entity and architecture names match, sensitivity list includes a, and port directions are correct.

3. Final Answer:

   Missing semicolon after b <= '1' -> Option A

4. Quick Check:

   Statements must end with semicolon [OK]

Hint: Check each statement ends with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing entity and architecture names
• Leaving sensitivity list empty

5. You want to create a VHDL module that has an entity with two inputs a and b and one output sum. The architecture should implement a simple 1-bit XOR gate. Which of the following architecture bodies correctly implements this behavior?

hard

A. architecture rtl of xor_gate is
begin
sum <= a and b;
end rtl;

B. architecture rtl of xor_gate is
begin
sum <= not (a and b);
end rtl;

C. architecture rtl of xor_gate is
begin
sum <= a or b;
end rtl;

D. architecture rtl of xor_gate is
begin
sum <= a xor b;
end rtl;

Solution

1. Step 1: Understand the required logic

   The output sum should be the XOR of inputs a and b.

2. Step 2: Match options to XOR behavior

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; uses a xor b, which is the correct XOR operation. Other options use AND, OR, or NAND-like logic.

3. Final Answer:

   architecture rtl of xor_gate is begin sum <= a xor b; end rtl; -> Option D

4. Quick Check:

   XOR gate uses 'xor' operator [OK]

Hint: XOR gate uses 'xor' keyword in architecture [OK]

Common Mistakes:

• Using 'and' or 'or' instead of 'xor'
• Confusing NOT with XOR
• Forgetting to assign output in architecture