Entity-Architecture model in VHDL - Step-by-Step Execution

Concept Flow - Entity-Architecture model

Start

↓

Define Entity

↓

Declare Ports

↓

Define Architecture

↓

Describe Behavior

↓

End Architecture

↓

Simulation or Synthesis

The flow starts by defining the entity with its ports, then the architecture describes the behavior, ending with simulation or synthesis.

Execution Sample

VHDL

entity AND_Gate is
  port(A, B: in std_logic;
       Y: out std_logic);
end AND_Gate;

architecture Behavioral of AND_Gate is
begin
  Y <= A and B;
end Behavioral;

This code defines an AND gate entity with inputs A, B and output Y, then describes its behavior in the architecture.

Execution Table

Step	Action	Entity Ports	Architecture Behavior	Output Y
1	Define entity AND_Gate with ports A, B (input), Y (output)	A: in, B: in, Y: out	Not started	Undefined
2	Start architecture Behavioral	Ports unchanged	Begin process	Undefined
3	Assign Y <= A and B	Ports unchanged	Y is assigned logical AND of A and B	Depends on A and B
4	Test with A='0', B='0'	A='0', B='0'	Y <= '0' and '0'	Y='0'
5	Test with A='0', B='1'	A='0', B='1'	Y <= '0' and '1'	Y='0'
6	Test with A='1', B='0'	A='1', B='0'	Y <= '1' and '0'	Y='0'
7	Test with A='1', B='1'	A='1', B='1'	Y <= '1' and '1'	Y='1'
8	End architecture	Ports unchanged	Behavior defined	Final output depends on inputs

💡 All input combinations tested; output Y reflects logical AND of inputs A and B.

Variable Tracker

Variable	Start	After Step 4	After Step 5	After Step 6	After Step 7	Final
A	Undefined	'0'	'0'	'1'	'1'	Varies
B	Undefined	'0'	'1'	'0'	'1'	Varies
Y	Undefined	'0'	'0'	'0'	'1'	Depends on A and B

Key Moments - 3 Insights

Why do we separate entity and architecture in VHDL?

Entity defines the interface (inputs/outputs), architecture defines the behavior. This separation allows reusing the same interface with different behaviors (see execution_table steps 1 and 3).

What happens if we change inputs A and B?

The output Y changes immediately according to the logic in architecture (see execution_table steps 4 to 7 showing output changes).

Can an entity have multiple architectures?

Yes, multiple architectures can describe different behaviors for the same entity interface, allowing flexible design reuse.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output Y when A=1 and B=0?

A Y=0

B Y=1

C Y=Undefined

D Y=Error

💡 Hint

Check execution_table row 6 where A=1 and B=0, output Y is 0.

At which step does the architecture start assigning output Y?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

See execution_table step 3 where Y is assigned as A and B.

If we add a new input C to the entity, how would the output Y assignment change?

A Y <= A xor B;

B Y <= A or B;

C Y <= A and B and C;

D No change needed

💡 Hint

Adding input C means output depends on A, B, and C; see architecture behavior in execution_table step 3.

Concept Snapshot

Entity-Architecture model in VHDL:
- Entity declares interface (inputs/outputs)
- Architecture describes behavior
- Ports connect entity and architecture
- Multiple architectures possible per entity
- Behavior defined by signal assignments inside architecture

Full Transcript

The Entity-Architecture model in VHDL separates the design into two parts: the entity defines the inputs and outputs, like a plug shape, and the architecture describes what the design does with those inputs to produce outputs. The example shows an AND gate entity with inputs A and B and output Y. The architecture assigns Y as the logical AND of A and B. The execution table traces how different input values affect output Y. This separation helps reuse and clarity in hardware design.