Multiplexer design in VHDL

Introduction

A multiplexer helps choose one input from many and sends it to the output. It saves wiring and makes circuits simpler.

When you want to select one signal out of many to send to a device.

When building digital circuits that need to switch between different data sources.

When designing communication systems to route signals efficiently.

When creating control units that decide which data path to use.

When you want to reduce the number of wires by sharing one output line.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
    Port (
        sel : in STD_LOGIC_VECTOR(n-1 downto 0);
        inputs : in STD_LOGIC_VECTOR(2**n-1 downto 0);
        output : out STD_LOGIC
    );
end mux;

architecture Behavioral of mux is
begin
    process(sel, inputs)
    begin
        case sel is
            when "00" => output <= inputs(0);
            when "01" => output <= inputs(1);
            when "10" => output <= inputs(2);
            when "11" => output <= inputs(3);
            when others => output <= '0';
        end case;
    end process;
end Behavioral;

The sel input chooses which input to send to the output.

The number of inputs is 2 to the power of the number of bits in sel.

Examples

This is a simple 2-to-1 multiplexer using a conditional assignment.

VHDL

entity mux2to1 is
    Port (
        sel : in STD_LOGIC;
        a, b : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux2to1;

architecture Behavioral of mux2to1 is
begin
    y <= a when sel = '0' else b;
end Behavioral;

This 4-to-1 multiplexer uses a process and a case statement to select the output.

VHDL

entity mux4to1 is
    Port (
        sel : in STD_LOGIC_VECTOR(1 downto 0);
        d0, d1, d2, d3 : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    process(sel, d0, d1, d2, d3)
    begin
        case sel is
            when "00" => y <= d0;
            when "01" => y <= d1;
            when "10" => y <= d2;
            when "11" => y <= d3;
            when others => y <= '0';
        end case;
    end process;
end Behavioral;

Sample Program

This program defines a 4-to-1 multiplexer and a testbench that changes the selector to show which input is passed to the output.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4to1 is
    Port (
        sel : in STD_LOGIC_VECTOR(1 downto 0);
        d0, d1, d2, d3 : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    process(sel, d0, d1, d2, d3)
    begin
        case sel is
            when "00" => y <= d0;
            when "01" => y <= d1;
            when "10" => y <= d2;
            when "11" => y <= d3;
            when others => y <= '0';
        end case;
    end process;
end Behavioral;

-- Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_mux4to1 is
end tb_mux4to1;

architecture Behavioral of tb_mux4to1 is
    signal sel : STD_LOGIC_VECTOR(1 downto 0) := "00";
    signal d0, d1, d2, d3 : STD_LOGIC := '0';
    signal y : STD_LOGIC;
begin
    uut: entity work.mux4to1
        port map(sel => sel, d0 => d0, d1 => d1, d2 => d2, d3 => d3, y => y);

    process
    begin
        d0 <= '0'; d1 <= '1'; d2 <= '0'; d3 <= '1';
        sel <= "00"; wait for 10 ns;
        report "sel=00, y=" & STD_LOGIC'image(y);
        sel <= "01"; wait for 10 ns;
        report "sel=01, y=" & STD_LOGIC'image(y);
        sel <= "10"; wait for 10 ns;
        report "sel=10, y=" & STD_LOGIC'image(y);
        sel <= "11"; wait for 10 ns;
        report "sel=11, y=" & STD_LOGIC'image(y);
        wait;
    end process;
end Behavioral;

Important Notes

Use process and case statements to clearly select inputs based on selector bits.

Remember to include all possible selector values and a default when others case to avoid latches.

Test your multiplexer with a testbench to verify it works as expected.

Summary

A multiplexer selects one input from many using selector bits.

In VHDL, use case inside a process or conditional assignments to design multiplexers.

Testing with different selector values ensures your design works correctly.