Multiplexer design in VHDL

Introduction

A multiplexer helps choose one input from many and sends it to the output. It saves wiring and makes circuits simpler.

When you want to select one signal out of many to send to a device.

When building digital circuits that need to switch between different data sources.

When designing communication systems to route signals efficiently.

When creating control units that decide which data path to use.

When you want to reduce the number of wires by sharing one output line.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
    Port (
        sel : in STD_LOGIC_VECTOR(n-1 downto 0);
        inputs : in STD_LOGIC_VECTOR(2**n-1 downto 0);
        output : out STD_LOGIC
    );
end mux;

architecture Behavioral of mux is
begin
    process(sel, inputs)
    begin
        case sel is
            when "00" => output <= inputs(0);
            when "01" => output <= inputs(1);
            when "10" => output <= inputs(2);
            when "11" => output <= inputs(3);
            when others => output <= '0';
        end case;
    end process;
end Behavioral;

The sel input chooses which input to send to the output.

The number of inputs is 2 to the power of the number of bits in sel.

Examples

This is a simple 2-to-1 multiplexer using a conditional assignment.

VHDL

entity mux2to1 is
    Port (
        sel : in STD_LOGIC;
        a, b : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux2to1;

architecture Behavioral of mux2to1 is
begin
    y <= a when sel = '0' else b;
end Behavioral;

This 4-to-1 multiplexer uses a process and a case statement to select the output.

VHDL

entity mux4to1 is
    Port (
        sel : in STD_LOGIC_VECTOR(1 downto 0);
        d0, d1, d2, d3 : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    process(sel, d0, d1, d2, d3)
    begin
        case sel is
            when "00" => y <= d0;
            when "01" => y <= d1;
            when "10" => y <= d2;
            when "11" => y <= d3;
            when others => y <= '0';
        end case;
    end process;
end Behavioral;

Sample Program

This program defines a 4-to-1 multiplexer and a testbench that changes the selector to show which input is passed to the output.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4to1 is
    Port (
        sel : in STD_LOGIC_VECTOR(1 downto 0);
        d0, d1, d2, d3 : in STD_LOGIC;
        y : out STD_LOGIC
    );
end mux4to1;

architecture Behavioral of mux4to1 is
begin
    process(sel, d0, d1, d2, d3)
    begin
        case sel is
            when "00" => y <= d0;
            when "01" => y <= d1;
            when "10" => y <= d2;
            when "11" => y <= d3;
            when others => y <= '0';
        end case;
    end process;
end Behavioral;

-- Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_mux4to1 is
end tb_mux4to1;

architecture Behavioral of tb_mux4to1 is
    signal sel : STD_LOGIC_VECTOR(1 downto 0) := "00";
    signal d0, d1, d2, d3 : STD_LOGIC := '0';
    signal y : STD_LOGIC;
begin
    uut: entity work.mux4to1
        port map(sel => sel, d0 => d0, d1 => d1, d2 => d2, d3 => d3, y => y);

    process
    begin
        d0 <= '0'; d1 <= '1'; d2 <= '0'; d3 <= '1';
        sel <= "00"; wait for 10 ns;
        report "sel=00, y=" & STD_LOGIC'image(y);
        sel <= "01"; wait for 10 ns;
        report "sel=01, y=" & STD_LOGIC'image(y);
        sel <= "10"; wait for 10 ns;
        report "sel=10, y=" & STD_LOGIC'image(y);
        sel <= "11"; wait for 10 ns;
        report "sel=11, y=" & STD_LOGIC'image(y);
        wait;
    end process;
end Behavioral;

Important Notes

Use process and case statements to clearly select inputs based on selector bits.

Remember to include all possible selector values and a default when others case to avoid latches.

Test your multiplexer with a testbench to verify it works as expected.

Summary

A multiplexer selects one input from many using selector bits.

In VHDL, use case inside a process or conditional assignments to design multiplexers.

Testing with different selector values ensures your design works correctly.

Practice

1. What is the main purpose of a multiplexer in VHDL design?

easy

A. To perform arithmetic operations on inputs

B. To store data temporarily

C. To select one input from multiple inputs and send it to the output

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer chooses one input from many inputs based on selector signals.

2. Step 2: Identify the correct purpose

   It outputs the selected input to a single output line.

3. Final Answer:

   To select one input from multiple inputs and send it to the output -> Option C

4. Quick Check:

   Multiplexer = input selector [OK]

Hint: Multiplexer picks one input to output [OK]

Common Mistakes:

• Confusing multiplexer with arithmetic unit
• Thinking multiplexer stores data
• Assuming multiplexer generates clocks

2. Which of the following is the correct way to declare a 4-to-1 multiplexer selector signal in VHDL?

easy

A. signal sel : integer range 0 to 3;

B. signal sel : std_logic_vector(3 downto 0);

C. signal sel : std_logic;

D. signal sel : std_logic_vector(1 downto 0);

Solution

1. Step 1: Determine selector size for 4 inputs

   For 4 inputs, selector needs 2 bits (log2(4) = 2).

2. Step 2: Match selector declaration

   std_logic_vector(1 downto 0) is 2 bits wide, correct for 4-to-1 mux.

3. Final Answer:

   signal sel : std_logic_vector(1 downto 0); -> Option D

4. Quick Check:

   2-bit selector for 4 inputs [OK]

Hint: Selector bits = log2(number of inputs) [OK]

Common Mistakes:

• Using 4 bits for selector of 4 inputs
• Using single bit for multiple inputs
• Using integer instead of std_logic_vector

3. Given the following VHDL code for a 2-to-1 multiplexer, what will be the output y when sel = '1' and inputs are a = '0', b = '1'?

process(sel, a, b)
begin
  if sel = '0' then
    y <= a;
  else
    y <= b;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. No output (error)

Solution

1. Step 1: Check selector value and inputs

   Selector sel = '1', inputs a = '0', b = '1'.

2. Step 2: Follow if-else logic

   If sel = '0', output y = a; else y = b. Since sel = '1', y = b = '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   sel=1 outputs b=1 [OK]

Hint: If sel=1 output b else a [OK]

Common Mistakes:

• Confusing sel '0' and '1' cases
• Assuming output is 'Z' (high impedance)
• Ignoring input values

4. Identify the error in this 4-to-1 multiplexer VHDL code snippet:

process(sel, d0, d1, d2, d3)
begin
  case sel is
    when "00" => y <= d0;
    when "01" => y <= d1;
    when "10" => y <= d2;
    when others => y <= d3;
  end case;
end process;

medium

A. Selector signal sel is not declared as 2 bits wide

B. Missing sensitivity list signals

C. Using 'when others' instead of explicit cases

D. Output y is not assigned in all cases

Solution

1. Step 1: Check selector declaration

   The code uses sel as 2-bit vector ("00", "01", "10"), so sel must be declared as std_logic_vector(1 downto 0).

2. Step 2: Identify missing or incorrect declaration

   If sel is not declared as 2 bits wide, the case statement will cause errors.

3. Final Answer:

   Selector signal sel is not declared as 2 bits wide -> Option A

4. Quick Check:

   Selector width must match case values [OK]

Hint: Selector width must match case patterns [OK]

Common Mistakes:

• Forgetting to declare selector width
• Leaving out signals in sensitivity list
• Misusing 'when others' in case

5. You want to design an 8-to-1 multiplexer in VHDL using a case statement. Which of the following selector signal declarations and case statement headers is correct?

hard

A. signal sel : std_logic;
...
case sel is
when '0' => ...
when '1' => ...

B. signal sel : std_logic_vector(2 downto 0);
...
case sel is
when "000" => ...
when "111" => ...

C. signal sel : std_logic_vector(1 downto 0);
...
case sel is
when "00" => ...
when "11" => ...

D. signal sel : std_logic_vector(3 downto 0);
...
case sel is
when "0000" => ...
when "0111" => ...

Solution

1. Step 1: Determine selector size for 8 inputs

   8 inputs require 3 bits selector (log2(8) = 3), so sel must be 3 bits wide.

2. Step 2: Match selector declaration and case values

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... uses std_logic_vector(2 downto 0) which is 3 bits, and case values from "000" to "111" which is correct.

3. Final Answer:

   signal sel : std_logic_vector(2 downto 0); ... case sel is when "000" => ... when "111" => ... -> Option B

4. Quick Check:

   3-bit selector for 8 inputs [OK]

Hint: Use 3-bit selector for 8 inputs [OK]

Common Mistakes:

• Using 4 bits for 8 inputs selector
• Using 1 or 2 bits for 8 inputs
• Mismatching case values and selector width