Type conversion functions in VHDL

Introduction

Type conversion functions help change data from one type to another so you can use it correctly in your program.

When you need to add a number stored as a string to an integer.

When you want to display a number but it is stored as a different type.

When you need to compare values of different types.

When you want to store a value in a variable of a different type.

When you want to convert a bit vector to an integer for calculations.

Syntax

VHDL

function TO_INTEGER(arg: UNSIGNED) return INTEGER;
function TO_STD_LOGIC_VECTOR(arg: UNSIGNED; size: NATURAL) return STD_LOGIC_VECTOR;

VHDL has built-in functions like TO_INTEGER and TO_STD_LOGIC_VECTOR for common conversions.

You must include the proper libraries like IEEE.NUMERIC_STD to use these functions.

Examples

Convert a std_logic_vector to integer by first converting it to unsigned.

VHDL

variable my_int : integer;
variable my_vec : std_logic_vector(7 downto 0);

my_int := TO_INTEGER(unsigned(my_vec));

Convert an integer to std_logic_vector by first converting it to unsigned with a size.

VHDL

variable my_vec : std_logic_vector(7 downto 0);
variable my_int : integer := 10;

my_vec := TO_STD_LOGIC_VECTOR(to_unsigned(my_int, 8));

Sample Program

This program converts a 4-bit vector "1010" to integer 10, then adds 5 and converts back to vector "1111".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity TypeConversionDemo is
end TypeConversionDemo;

architecture Behavioral of TypeConversionDemo is
begin
    process
        variable vec : std_logic_vector(3 downto 0) := "1010";
        variable num : integer;
        variable vec2 : std_logic_vector(3 downto 0);
    begin
        -- Convert std_logic_vector to integer
        num := TO_INTEGER(unsigned(vec));
        report "Converted vector to integer: " & integer'image(num);

        -- Convert integer back to std_logic_vector
        vec2 := std_logic_vector(to_unsigned(num + 5, 4));
        report "Converted integer+5 back to vector: " & vec2;

        wait;
    end process;
end Behavioral;

Important Notes

Always convert std_logic_vector to unsigned or signed before converting to integer.

Size must be specified when converting integer to std_logic_vector.

Type conversion functions help avoid errors when mixing data types.

Summary

Type conversion functions change data from one type to another.

Use IEEE.NUMERIC_STD library for conversions between std_logic_vector and integer.

Always match sizes and types carefully to avoid errors.